|
[PML Ver]			2.1
[Comment Char]		|_char
[File Rev]			1.0
[Date]				February 27, 1997
[Source]			Created by HyperLynx, Inc.
[Notes]        Created by HyperLynx, Inc.
[Disclaimer] 
|
    The user is granted a license only to use this PML
model in conjunction with HyperLynx software and is not 
granted rights to sell, rent, lease or license the PML 
model in whole or in part, or in modified form to anyone
other than user. User may modify the PML model to suit
specific applications but rights to derivative works and
such modifications shall belong to HyperLynx, Inc.
|
    Although HyperLynx has made reasonable efforts to ensure
the accuracy and quality of this PML model, the model is 
provided on an "AS IS" basis and HyperLynx makes absolutely 
no warranty with respect to the information contained herein.
HyperLynx disclaims and the user waives all warranties, 
express or implied, including warranties of merchantability 
of fitness for a particular prupose. The entire risk as to 
quality and performance is with the user. Accordingly, in no 
event shall HyperLynx be liable for any damages, including
any lost profits or any other incidental, consequential,
exemplary, or punitive damages arising out of the use or
application of the PML model provided in this package.
|
[Copyright]			Copyright 1997, HyperLynx, Inc.  All rights reserved.
|
|==============================================================================
| Note:	The [Contents] record must precede all [Package] and [Component]
|			records in the file
|==============================================================================
[Contents]
74HC00_DIP
74HC00_SOIC
74HC00_SSOP
74HC00_TSSOP
74HC02_DIP
74HC02_SOIC
74HC02_SSOP
74HC02_TSSOP
74HC03_DIP
74HC03_SOIC
74HC03_SSOP
74HC03_TSSOP
74HC04_DIP
74HC04_SOIC
74HC04_SSOP
74HC04_TSSOP
74HC05_DIP
74HC05_SOIC
74HC05_SSOP
74HC05_TSSOP
74HC08_DIP
74HC08_SOIC
74HC08_SSOP
74HC08_TSSOP
74HC10_DIP
74HC10_SOIC
74HC10_SSOP
74HC10_TSSOP
74HC11_DIP
74HC11_SOIC
74HC11_SSOP
74HC11_TSSOP
74HC14_DIP
74HC14_SOIC
74HC14_SSOP
74HC14_TSSOP
74HC20_DIP
74HC20_SOIC
74HC20_SSOP
74HC20_TSSOP
74HC21_DIP
74HC21_SOIC
74HC21_SSOP
74HC21_TSSOP
74HC27_DIP
74HC27_SOIC
74HC27_SSOP
74HC27_TSSOP
74HC30_DIP
74HC30_SOIC
74HC30_SSOP
74HC30_TSSOP
74HC32_DIP
74HC32_SOIC
74HC32_SSOP
74HC32_TSSOP
74HC36_DIP
74HC36_SOIC
74HC36_SSOP
74HC36_TSSOP
74HC42_DIP
74HC42_SOIC
74HC42_SSOP
74HC51_DIP
74HC51_SOIC
74HC51_SSOP
74HC51_TSSOP
74HC51_DIP
74HC51_SOIC
74HC51_SSOP
74HC51_TSSOP
74HC58_DIP
74HC58_SOIC
74HC58_SSOP
74HC58_TSSOP
74HC73_DIP
74HC73_SOIC
74HC73_SSOP
74HC73_TSSOP
74HC74_DIP
74HC74_SOIC
74HC74_SSOP
74HC74_TSSOP
74HC75_DIP
74HC75_SOIC
74HC75_SSOP
74HC76_DIP
74HC76_SOIC
74HC76_SSOP
74HC78_DIP
74HC78_SOIC
74HC78_SSOP
74HC78_TSSOP
74HC85_DIP
74HC85_SOIC
74HC85_SSOP
74HC86_DIP
74HC86_SOIC
74HC86_SSOP
74HC86_TSSOP
74HC107_DIP
74HC107_SOIC
74HC107_SSOP
74HC107_TSSOP
74HC109_DIP
74HC109_SOIC
74HC109_SSOP
74HC112_DIP
74HC112_SOIC
74HC112_SSOP
74HC113_DIP
74HC113_SOIC
74HC113_SSOP
74HC113_TSSOP
74HC114_DIP
74HC114_SOIC
74HC114_SSOP
74HC114_TSSOP
74HC123_DIP
74HC123_SSOP
74HC125_DIP
74HC125_SOIC
74HC125_SSOP
74HC125_TSSOP
74HC126_DIP
74HC126_SOIC
74HC126_SSOP
74HC126_TSSOP
74HC132_DIP
74HC132_SOIC
74HC132_SSOP
74HC132_TSSOP
74HC133_DIP
74HC133_SOIC
74HC133_SSOP
74HC137_DIP
74HC137_SOIC
74HC137_SSOP
74HC138_DIP
74HC138_SOIC
74HC138_SSOP
74HC139_DIP
74HC139_SSOP
74HC147_DIP
74HC147_SSOP
74HC148_DIP
74HC148_SSOP
74HC151_DIP
74HC151_SOIC
74HC151_SSOP
74HC152_DIP
74HC152_SOIC
74HC152_SSOP
74HC152_TSSOP
74HC153_DIP
74HC153_SOIC
74HC153_SSOP
74HC154_DIP
74HC154_SOIC
74HC154_SSOP
74HC154_TSSOP
74HC157_DIP
74HC157_SOIC
74HC157_SSOP
74HC158_DIP
74HC158_SOIC
74HC158_SSOP
74HC160_DIP
74HC160_SOIC
74HC160_SSOP
74HC161_DIP
74HC161_SOIC
74HC161_SSOP
74HC162_DIP
74HC162_SOIC
74HC162_SSOP
74HC163_DIP
74HC163_SSOP
74HC164_DIP
74HC164_SOIC
74HC164_SSOP
74HC164_TSSOP
74HC165_DIP
74HC165_SOIC
74HC165_SSOP
74HC166_DIP
74HC166_SOIC
74HC166_SSOP
74HC169_DIP
74HC169_SSOP
74HC173_DIP
74HC173_SOIC
74HC173_SSOP
74HC174_DIP
74HC174_SOIC
74HC174_SSOP
74HC175_DIP
74HC175_SOIC
74HC175_SSOP
74HC180_DIP
74HC180_SOIC
74HC180_SSOP
74HC180_TSSOP
74HC181_DIP
74HC181_SOIC
74HC181_SSOP
74HC181_TSSOP
74HC182_DIP
74HC182_SSOP
74HC190_DIP
74HC190_SOIC
74HC190_SSOP
74HC191_DIP
74HC191_SOIC
74HC191_SSOP
74HC192_DIP
74HC192_SOIC
74HC192_SSOP
74HC193_DIP
74HC193_SOIC
74HC193_SSOP
74HC194_DIP
74HC194_SOIC
74HC194_SSOP
74HC195_DIP
74HC195_SOIC
74HC195_SSOP
74HC221_DIP
74HC221_SSOP
74HC237_DIP
74HC237_SOIC
74HC237_SSOP
74HC238_DIP
74HC238_SOIC
74HC238_SSOP
74HC239_DIP
74HC239_SOIC
74HC239_SSOP
74HC240_DIP
74HC240_SOIC
74HC240_SSOP
74HC240_TSSOP
74HC241_DIP
74HC241_SOIC
74HC241_SSOP
74HC241_TSSOP
74HC242_DIP
74HC242_SOIC
74HC242_SSOP
74HC242_TSSOP
74HC243_DIP
74HC243_SOIC
74HC243_SSOP
74HC243_TSSOP
74HC244_DIP
74HC244_SOIC
74HC244_SSOP
74HC244_TSSOP
74HC245_DIP
74HC245_SOIC
74HC245_SSOP
74HC245_TSSOP
74HC251_DIP
74HC251_SOIC
74HC251_SSOP
74HC253_DIP
74HC253_SOIC
74HC253_SSOP
74HC257_DIP
74HC257_SSOP
74HC258_DIP
74HC258_SOIC
74HC258_SSOP
74HC259_DIP
74HC259_SOIC
74HC259_SSOP
74HC260_DIP
74HC260_SOIC
74HC260_SSOP
74HC260_TSSOP
74HC266_DIP
74HC266_SOIC
74HC266_SSOP
74HC266_TSSOP
74HC266_DIP
74HC266_SOIC
74HC266_SSOP
74HC266_TSSOP
74HC273_DIP
74HC273_SOIC
74HC273_SSOP
74HC273_TSSOP
74HC280_DIP
74HC280_SOIC
74HC280_SSOP
74HC280_TSSOP
74HC283_DIP
74HC283_SOIC
74HC283_SSOP
74HC292_DIP
74HC292_SSOP
74HC294_DIP
74HC294_SSOP
74HC298_DIP
74HC298_SOIC
74HC298_SSOP
74HC299_DIP
74HC299_SOIC
74HC299_SSOP
74HC299_TSSOP
74HC323_DIP
74HC323_SOIC
74HC323_SSOP
74HC323_TSSOP
74HC352_DIP
74HC352_SOIC
74HC352_SSOP
74HC353_DIP
74HC353_SOIC
74HC353_SSOP
74HC354_DIP
74HC354_SOIC
74HC354_SSOP
74HC354_TSSOP
74HC356_DIP
74HC356_SOIC
74HC356_SSOP
74HC356_TSSOP
74HC365_DIP
74HC365_SOIC
74HC365_SSOP
74HC366_DIP
74HC366_SOIC
74HC366_SSOP
74HC367_DIP
74HC367_SOIC
74HC367_SSOP
74HC368_DIP
74HC368_SOIC
74HC368_SSOP
74HC373_DIP
74HC373_SOIC
74HC373_SSOP
74HC373_TSSOP
74HC374_DIP
74HC374_SOIC
74HC374_SSOP
74HC374_TSSOP
74HC375_DIP
74HC375_SOIC
74HC375_SSOP
74HC377_DIP
74HC377_SOIC
74HC377_SSOP
74HC377_TSSOP
74HC378_DIP
74HC378_SOIC
74HC378_SSOP
74HC379_DIP
74HC379_SOIC
74HC379_SSOP
74HC386_DIP
74HC386_SOIC
74HC386_SSOP
74HC386_TSSOP
74HC390_DIP
74HC390_SOIC
74HC390_SSOP
74HC393_DIP
74HC393_SOIC
74HC393_SSOP
74HC393_TSSOP
74HC423_DIP
74HC423_SSOP
74HC490_DIP
74HC490_SOIC
74HC490_SSOP
74HC521_DIP
74HC521_SOIC
74HC521_SSOP
74HC521_TSSOP
74HC533_DIP
74HC533_SOIC
74HC533_SSOP
74HC533_TSSOP
74HC534_DIP
74HC534_SOIC
74HC534_SSOP
74HC534_TSSOP
74HC540_DIP
74HC540_SOIC
74HC540_SSOP
74HC540_TSSOP
74HC541_DIP
74HC541_SOIC
74HC541_SSOP
74HC541_TSSOP
74HC543_DIP
74HC543_SOIC
74HC543_SSOP
74HC543_TSSOP
74HC544_DIP
74HC544_SOIC
74HC544_SSOP
74HC544_TSSOP
74HC550_DIP
74HC550_SOIC
74HC550_SSOP
74HC551_DIP
74HC551_SOIC
74HC551_SSOP
74HC563_DIP
74HC563_SOIC
74HC563_SSOP
74HC563_TSSOP
74HC564_DIP
74HC564_SOIC
74HC564_SSOP
74HC564_TSSOP
74HC573_DIP
74HC573_SOIC
74HC573_SSOP
74HC573_TSSOP
74HC574_DIP
74HC574_SOIC
74HC574_SSOP
74HC574_TSSOP
74HC589_DIP
74HC589_SSOP
74HC590_DIP
74HC590_SOIC
74HC590_SSOP
74HC592_DIP
74HC592_SSOP
74HC593_DIP
74HC593_SOIC
74HC593_SSOP
74HC593_TSSOP
74HC594_DIP
74HC594_SOIC
74HC594_SSOP
74HC595_DIP
74HC595_SOIC
74HC595_SSOP
74HC597_DIP
74HC597_SSOP
74HC604_DIP
74HC604_SOIC
74HC604_SSOP
74HC620_DIP
74HC620_SOIC
74HC620_SSOP
74HC620_TSSOP
74HC623_DIP
74HC623_SOIC
74HC623_SSOP
74HC623_TSSOP
74HC640_DIP
74HC640_SOIC
74HC640_SSOP
74HC640_TSSOP
74HC643_DIP
74HC643_SOIC
74HC643_SSOP
74HC643_TSSOP
74HC645_DIP
74HC645_SOIC
74HC645_SSOP
74HC645_TSSOP
74HC646_DIP
74HC646_SOIC
74HC646_SSOP
74HC646_TSSOP
74HC648_DIP
74HC648_SOIC
74HC648_SSOP
74HC648_TSSOP
74HC651_DIP
74HC651_SOIC
74HC651_SSOP
74HC651_TSSOP
74HC652_DIP
74HC652_SOIC
74HC652_SSOP
74HC652_TSSOP
74HC652_DIP
74HC652_SOIC
74HC652_SSOP
74HC652_TSSOP
74HC658_DIP
74HC658_SOIC
74HC658_SSOP
74HC658_TSSOP
74HC659_DIP
74HC659_SOIC
74HC659_SSOP
74HC659_TSSOP
74HC664_DIP
74HC664_SOIC
74HC664_SSOP
74HC664_TSSOP
74HC665_DIP
74HC665_SOIC
74HC665_SSOP
74HC665_TSSOP
74HC677_DIP
74HC677_SOIC
74HC677_SSOP
74HC677_TSSOP
74HC678_DIP
74HC678_SOIC
74HC678_SSOP
74HC678_TSSOP
74HC679_DIP
74HC679_SOIC
74HC679_SSOP
74HC679_TSSOP
74HC680_DIP
74HC680_SOIC
74HC680_SSOP
74HC680_TSSOP
74HC682_DIP
74HC682_SOIC
74HC682_SSOP
74HC682_TSSOP
74HC684_DIP
74HC684_SOIC
74HC684_SSOP
74HC684_TSSOP
74HC688_DIP
74HC688_SOIC
74HC688_SSOP
74HC688_TSSOP
74HC804_DIP
74HC804_SOIC
74HC804_SSOP
74HC804_TSSOP
74HC805_DIP
74HC805_SOIC
74HC805_SSOP
74HC805_TSSOP
74HC808_DIP
74HC808_SOIC
74HC808_SSOP
74HC808_TSSOP
74HC832_DIP
74HC832_SOIC
74HC832_SSOP
74HC832_TSSOP
74HC4002_DIP
74HC4002_SOIC
74HC4002_SSOP
74HC4002_TSSOP
74HC4017_DIP
74HC4017_SOIC
74HC4017_SSOP
74HC4020_DIP
74HC4020_SOIC
74HC4020_SSOP
74HC4024_DIP
74HC4024_SOIC
74HC4024_SSOP
74HC4024_TSSOP
74HC4040_DIP
74HC4040_SOIC
74HC4040_SSOP
74HC4046_DIP
74HC4046_SSOP
74HC4049_DIP
74HC4049_SSOP
74HC4050_DIP
74HC4050_SSOP
74HC4051_DIP
74HC4051_SSOP
74HC4052_DIP
74HC4052_SSOP
74HC4053_DIP
74HC4053_SSOP
74HC4060_DIP
74HC4060_SOIC
74HC4060_SSOP
74HC4061_DIP
74HC4061_SOIC
74HC4061_SSOP
74HC4075_DIP
74HC4075_SOIC
74HC4075_SSOP
74HC4075_TSSOP
74HC4078_DIP
74HC4078_SOIC
74HC4078_SSOP
74HC4078_TSSOP
74HC4351_DIP
74HC4352_DIP
74HC4353_DIP
74HC4514_DIP
74HC4514_SOIC
74HC4514_SSOP
74HC4514_TSSOP
74HC4515_DIP
74HC4515_SOIC
74HC4515_SSOP
74HC4515_TSSOP
74HC4538_DIP
74HC4538_SSOP
74HC4724_DIP
74HC4724_SOIC
74HC4724_SSOP
74HC7001_DIP
74HC7001_SOIC
74HC7001_SSOP
74HC7001_TSSOP
74HC7002_DIP
74HC7002_SOIC
74HC7002_SSOP
74HC7002_TSSOP
74HC7006_DIP
74HC7006_SOIC
74HC7006_SSOP
74HC7006_TSSOP
74HC7008_DIP
74HC7008_SOIC
74HC7008_SSOP
74HC7008_TSSOP
74HC7022_DIP
74HC7022_SOIC
74HC7022_SSOP
74HC7032_DIP
74HC7032_SOIC
74HC7032_SSOP
74HC7032_TSSOP
74HC7074_DIP
74HC7074_SOIC
74HC7074_SSOP
74HC7074_TSSOP
74HC7075_DIP
74HC7075_SOIC
74HC7075_SSOP
74HC7075_TSSOP
74HC7076_DIP
74HC7076_SOIC
74HC7076_SSOP
74HC7076_TSSOP
74HC7266_DIP
74HC7266_SOIC
74HC7266_SSOP
74HC7266_TSSOP
|
|
| [Family] is only included in the Master File.  This is used for sorting
|			purposes and is deleted when the individual family libraries are 
|            created.
|
| ENBO == Enable-able Output, used in tri-state output devices
|			where output is not shared with input on same pin (i.e. SN74LS244)
| IN   == input only
| OUT  == output only
| BIDIR == input/output, used in line drivers where a single pin is 
|			used as input/output (i.e. SN74LS245)
|
| MODEL_NAMES;
|
|	GATE == input or output of a logic gate (low output current, <12mA)
|	LINE-DRV == high output current, above 24mA both high and low currents
|	OPEN-COL == open collector output
|
|***********FOR FUTURE USE NOT CURRENTLY IMPLEMENTED**********************   
|  
|	OPEN-DRN == open drain on output pin
|	ANALOG  == Analog signals
|   RSWITCH:RESISTANCE:PIN:PIN2 ==
|					 series resistance attached to a pin where PIN2 is the
|					 terminating pin.
|*************************************************************************
|
| SIGNAL_NAME:  A minus sign ( - ) directly following a signal_name is used to signify
|						a bar over the signal_name (i.e. Q- is "Q not" or "Q bar")
|	
|  The [Package]  DIP52-TI and DIP48-TI packages are from a 56 pin with the 
|                  ends "cut off"
|
|	SOIC 
|	TVSOP  Thin Very  Small Outline Package	**This is not currently in use**
|	TSSOP  Thin Shrink Small Outline Package  
|	SSOP   Shrink Small Outline Package
|
|==============================================================================
|==============================================================================
| Note:	[Package] records must precede all [Component] records in the file
|==============================================================================
|==============================================================================
[Package]			DIP14
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			400.0m	6.1nH		1.17pF
2			300.0m	2.9nH		1.03pF
3			300.0m	2.9nH		1.03pF
4			300.0m	2.5nH		0.89pF
5			300.0m	3.6nH		1.03pF
6			300.0m	5.1nH		1.23pF
7			400.0m	7.3nH		1.17pF
8			400.0m	7.3nH		1.17pF
9			300.0m	5.1nH		1.23pF
10			300.0m	3.6nH		1.03pF
11			300.0m	2.5nH		0.89pF
12			300.0m	2.9nH		1.03pF
13			300.0m	2.9nH		1.03pF
14			400.0m	6.1nH		1.17pF
|
|==============================================================================
|==============================================================================
[Package]			DIP16
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			400.0m	7.0nH		1.40pF
2			400.0m	4.6nH		1.09pF
3			400.0m	3.2nH		1.09pF
4			300.0m	2.6nH		0.72pF
5			300.0m	2.9nH		0.72pF
6			400.0m	4.0nH		1.09pF
7			400.0m	5.6nH		1.09pF
8			400.0m	8.2nH		1.40pF
9			400.0m	8.2nH		1.40pF
10			400.0m	5.6nH		1.09pF
11			400.0m	4.0nH		1.09pF
12			300.0m	2.9nH		0.72pF
13			300.0m	2.6nH		0.72pF
14			400.0m	3.2nH		1.09pF
15			400.0m	4.6nH		1.09pF
16			400.0m	7.0nH		1.40pF
|
|==============================================================================
|==============================================================================
[Package]			DIP18
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			300.0m	7.8nH		1.5pF
2			300.0m	5.8nH		1.17pF
3			400.0m	4.3nH		1.18pF
4			300.0m	2.6nH		0.89pF
5			300.0m	2.4nH		0.89pF
6			300.0m	3.3nH		1.18pF
7			300.0m	4.7nH		1.17pF
8			300.0m	6.4nH		1.50pF
9			300.0m	8.9nH		1.81pF
10			300.0m	8.9nH		1.81pF
11			300.0m	6.4nH		1.50pF
12			300.0m	4.7nH		1.17pF
13			300.0m	3.3nH		1.18pF
14			300.0m	2.4nH		0.89pF
15			300.0m	2.6nH		0.89pF
16			400.0m	4.3nH		1.18pF
17			300.0m	5.8nH		1.17pF
18			300.0m	7.8nH		1.5pF
|
|==============================================================================
|==============================================================================
[Package]			DIP20
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			400.0m	10.2nH	1.81pF
2			300.0m	7.8nH		1.5pF
3			300.0m	5.8nH		1.17pF
4			400.0m	4.3nH		1.18pF
5			300.0m	2.6nH		0.89pF
6			300.0m	2.4nH		0.89pF
7			300.0m	3.3nH		1.18pF
8			300.0m	4.7nH		1.17pF
9			300.0m	6.4nH		1.50pF
10			300.0m	8.9nH		1.81pF
11			300.0m	8.9nH		1.81pF
12			300.0m	6.4nH		1.50pF
13			300.0m	4.7nH		1.17pF
14			300.0m	3.3nH		1.18pF
15			300.0m	2.4nH		0.89pF
16			300.0m	2.6nH		0.89pF
17			400.0m	4.3nH		1.18pF
18			300.0m	5.8nH		1.17pF
19			300.0m	7.8nH		1.5pF
20			400.0m	10.2nH	1.81pF
|
|==============================================================================
|==============================================================================
[Package]			DIP24
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			400.0m	13.2nH	2.16pF
2			300.0m	10.5nH	1.84pF
3			300.0m	8.0nH		1.43pF
4			400.0m	6.0nH		1.20pF
5			300.0m	3.8nH		0.91pF
6			300.0m	2.5nH		0.69pF
7			300.0m	2.2nH		0.69pF
8			300.0m	3.1nH		0.91pF
9			300.0m	4.8nH		1.20pF
10			300.0m	6.8nH		1.43pF
11			300.0m	9.2nH		1.84pF
12			300.0m	11.9nH	2.16pF
13			300.0m	11.9nH	2.16pF
14			300.0m	9.2nH		1.84pF
15			300.0m	6.8nH		1.43pF
16			300.0m	4.8nH		1.20pF
17			400.0m	3.1nH		0.91pF
18			300.0m	2.2nH		0.69pF
19			300.0m	2.5nH		0.69pF
20			400.0m	3.8nH		0.91pF
21			400.0m	6.0nH		1.20pF
22			400.0m	8.0nH		1.43pF
23			400.0m	10.5nH	1.84pF
24			400.0m	13.2nH	2.16pF
|
|==============================================================================
|==============================================================================
[Package]			DIP28
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1       .12       5.04n    .59p   
2       .12       5.04n    .59p
3       .1        4.6n     .57p	   
4       .1        4.6n     .57p	
5       .12       5.04n    .59p 
6       .11       4.63n    .54p 
7       .12       5.04n    .57p 
8       .14       5.38n    .59p 
9       .12       5.04n    .59p  
10      .11       4.63n    .57p 
11      .1        4.6n     .54p 
12      .1        4.6n     .54p 
13      .12       5.04n    .59p
14      .12       5.04n    .59p 
15      .12       5.04n    .59p 
16      .12       5.04n    .59p
17      .1        4.6n     .54p 
18      .1        4.6n     .54p 
19      .1        4.6n     .54p
20      .12       5.04n    .59p  
21      .12       5.04n    .59p
22      .14       5.38n    .59p 
23      .12       5.04n    .59p 
24      .12       5.04n    .59p 
25      .1        4.6n     .54p 
26      .1        4.6n     .54p	
27      .12       5.04n    .59p 
28      .12       5.04n    .59p 
|
|==============================================================================
|==============================================================================
[Package]			DIP48
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			10m	   6.96n		0.74p
2			10m	   6.25n		0.71p
3			10m	   4.71n		0.59p
4			10m	   4.71n		0.59p
5			10m	   4.39n		0.48p
6			10m	   4.12n		0.45p
7			10m	   3.81n		0.41p
8			10m	   3.57n		0.38p
9			10m	   3.40n		0.35p
10			10m	   3.13n		0.30p
11			10m      3.13n		0.30p
12			10m	   3.07n		0.28p
13			10m	   3.07n		0.28p
14			10m		3.13n		0.30p
15			10m		3.23n		0.32p
16			10m		3.40n		0.35p
17			10m		3.57n		0.38p
18			10m		3.81n		0.41p
19			10m		4.12n		0.45p
20			10m		4.39n		0.48p
21			10m		4.71n		0.59p
22			10m		5.43n		0.69p
23			10m		6.25n		0.71p
24			10m		6.96n		0.74p
25			10m		6.96n		0.74p
26			10m		6.25n		0.71p
27			10m		5.43n		0.69p
28			10m		4.71n		0.59p
29			10m		4.39n		0.48p
30			10m		4.12n		0.45p
31			10m		3.81n		0.41p
32			10m		3.57n		0.38p
33			10m		3.40n		0.35p
34			10m		3.23n		0.32p
35			10m		3.07n		0.28p
36			10m		3.07n		0.28p
37			10m		3.07n		0.28p
38			10m		3.13n		0.30p
39			10m		3.23n		0.32p
40			10m		3.40n		0.35p
41			10m		3.81n		0.42p
42		   10m		3.81n		0.45p
43			10m		4.12n		0.45p
44			10m		4.39n		0.48p
45			10m		4.71n		0.59p
46			10m		5.43n		0.69p
47			10m		6.25n		0.71p
48			10m		6.96n		0.74p
|
|==============================================================================
|==============================================================================
[Package]			DIP52
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			10m      7.76n		0.77p
2			10m      6.96n		0.74p
3			10m      6.25n		0.71p
4			10m      4.71n		0.59p
5			10m      4.71n		0.59p
6			10m      4.39n		0.48p
7			10m      4.12n		0.45p
8			10m      3.81n		0.41p
9			10m      3.57n		0.38p
10			10m      3.40n		0.35p
11			10m      3.13n		0.30p
12			10m      3.13n		0.30p
13			10m      3.07n		0.28p
14			10m      3.07n		0.28p
15			10m		3.13n		0.30p
16			10m		3.23n		0.32p
17			10m		3.40n		0.35p
18			10m		3.57n		0.38p
19			10m		3.81n		0.41p
20			10m		4.12n		0.45p
21			10m		4.39n		0.48p
22			10m		4.71n		0.59p
23			10m		5.43n		0.69p
24			10m		6.25n		0.71p
25			10m		6.96n		0.74p
26			10m		7.76n		0.77p
27			10m		7.76n		0.77p
28			10m		6.96n		0.74p
29			10m		6.25n		0.71p
30			10m		5.43n		0.69p
31			10m		4.71n		0.59p
32			10m		4.39n		0.48p
33			10m		4.12n		0.45p
34			10m		3.81n		0.41p
35			10m		3.57n		0.38p
36			10m		3.40n		0.35p
37			10m		3.23n		0.32p
38			10m		3.07n		0.28p
39			10m		3.07n		0.28p
40			10m		3.07n		0.28p
41			10m		3.13n		0.30p
42			10m		3.23n		0.32p
43			10m		3.40n		0.35p
44			10m		3.81n		0.42p
45			10m		3.81n		0.45p
46			10m		4.12n		0.45p
47			10m		4.39n		0.48p
48			10m		4.71n		0.59p
49			10m		5.43n		0.69p
50			10m		6.25n		0.71p
51			10m		6.96n		0.74p
52			10m		7.76n		0.77p
|
|==============================================================================
|==============================================================================
[Package]			DIP56
Type	DIP
|
Pin		R_pin		L_pin		C_pin
|
1			10m      8.63n		0.80p
2		   10m      7.76n		0.77p
3		   10m      6.96n		0.74p
4		   10m      6.25n		0.71p
5			10m      4.71n		0.59p
6		   10m      4.71n		0.59p
7		   10m      4.39n		0.48p
8			10m      4.12n		0.45p
9		   10m      3.81n		0.41p
10		   10m      3.57n		0.38p
11			10m      3.40n		0.35p
12		   10m      3.13n		0.30p
13		   10m      3.13n		0.30p
14			10m      3.07n		0.28p
15		   10m      3.07n		0.28p
16		   10m		3.13n		0.30p
17			10m		3.23n		0.32p
18	      10m		3.40n		0.35p
19		   10m		3.57n		0.38p
20			10m		3.81n		0.41p
21		   10m		4.12n		0.45p
22		   10m		4.39n		0.48p
23		   10m		4.71n		0.59p
24		   10m		5.43n		0.69p
25			10m		6.25n		0.71p
26			10m		6.96n		0.74p
27			10m		7.76n		0.77p
28		   10m		8.62n		0.80p
29		   10m		8.62n		0.80p
30			10m		7.76n		0.77p
31 	   10m		6.96n		0.74p
32		   10m		6.25n		0.71p
33		   10m		5.43n		0.69p
34		   10m		4.71n		0.59p
35			10m		4.39n		0.48p
36		   10m		4.12n		0.45p
37		   10m	 	3.81n		0.41p
38			10m		3.57n		0.38p
39		   10m		3.40n		0.35p
40		   10m		3.23n		0.32p
41			10m		3.07n		0.28p
42		   10m		3.07n		0.28p
43		   10m		3.07n		0.28p
44			10m		3.13n		0.30p
45		   10m		3.23n		0.32p
46		   10m		3.40n		0.35p
47		   10m		3.81n		0.42p
48			10m		3.81n		0.45p
49		   10m		4.12n		0.45p
50		   10m		4.39n		0.48p
51			10m		4.71n		0.59p
52		   10m		5.43n		0.69p
53		   10m		6.25n		0.71p
54			10m		6.96n		0.74p
55	      10m		7.76n		0.77p
56		   10m		8.62n		0.80p
|	
|==============================================================================
|==============================================================================
[Package]		SOIC14
Type		SOIC
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		3.8nH		0.54pF
2			0.0		3.4nH		0.39pF
3			0.0		3.0nH		0.22pF
4			0.0		2.6nH		0.22pF
5			0.0		3.0nH		0.22pF
6			0.0		3.4nH		0.39pF
7			0.0		3.8nH		0.54pF
8			0.0		3.8nH		0.54pF		
9			0.0		3.4nH		0.39pF		
10			0.0		3.0nH		0.22pF		
11			0.0		2.6nH		0.22pF		
12			0.0		3.0nH		0.22pF		
13			0.0		3.4nH		0.39pF		
14			0.0		3.8nH		0.54pF		
|
|==============================================================================
|==============================================================================
[Package]		SOIC16
Type		SOIC
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		3.77nH	0.60pF
2			0.0		3.28nH	0.54pF
3			0.0		3.03nH	0.45pF
4			0.0		3.03nH	0.45pF
5			0.0		3.28nH	0.54pF
6			0.0		3.77nH	0.60pF
7			0.0		4.56nH	0.75pF
8			0.0		5.84nH	0.85pF
9			0.0		5.84nH	0.85pF		
10			0.0		4.56nH	0.75pF		
11			0.0		3.77nH	0.60pF		
12			0.0		3.28nH	0.54pF		
13			0.0		3.03nH	0.45pF		
14			0.0		3.03nH	0.45pF		
15			0.0		3.28nH	0.54pF		
16			0.0		3.77nH	0.60pF		
|
|==============================================================================
|==============================================================================
[Package]		SOIC20
Type		SOIC
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		5.84nH	0.85pF
2			0.0		4.56nH	0.75pF
3			0.0		3.77nH	0.60pF
4			0.0		3.28nH	0.54pF
5			0.0		3.03nH	0.45pF
6			0.0		3.03nH	0.45pF
7			0.0		3.28nH	0.54pF
8			0.0		3.77nH	0.60pF
9			0.0		4.56nH	0.75pF
10			0.0		5.84nH	0.85pF
11			0.0		5.84nH	0.85pF		
12			0.0		4.56nH	0.75pF		
13			0.0		3.77nH	0.60pF		
14			0.0		3.28nH	0.54pF		
15			0.0		3.03nH	0.45pF		
16			0.0		3.03nH	0.45pF		
17			0.0		3.28nH	0.54pF		
18			0.0		3.77nH	0.60pF		
19			0.0		4.56nH	0.75pF		
20			0.0		5.84nH	0.85pF		
|
|==============================================================================
|==============================================================================
[Package]		SOIC24
Type		SOIC
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		6.77nH	0.98pF
2			0.0		5.20nH	0.92pF
3			0.0		4.10nH	0.64pF
4			0.0		3.37nH	0.55pF
5			0.0		2.95nH	0.46pF
6			0.0		2.83nH	0.40pF
7			0.0		2.83nH	0.40pF
8			0.0		2.95nH	0.46pF
9			0.0		3.37nH	0.55pF
10			0.0		4.10nH	0.64pF
11			0.0		5.20nH	0.92pF
12			0.0		6.77nH	0.98pF
13			0.0		6.77nH	0.98pF		
14			0.0		5.20nH	0.92pF		
15			0.0		4.10nH	0.64pF		
16			0.0		3.37nH	0.55pF		
17			0.0		2.95nH	0.46pF		
18			0.0		2.83nH	0.40pF		
19			0.0		2.83nH	0.40pF		
20			0.0		2.95nH	0.46pF		
21			0.0		3.37nH	0.55pF		
22			0.0		4.10nH	0.64pF		
23			0.0		5.20nH	0.92pF		
24			0.0		6.77nH	0.98pF		
|
|==============================================================================
|==============================================================================
[Package]		SOIC28
Type		SOIC
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		8.15nH	1.06pF
2			0.0		6.75nH	0.98pF
3			0.0		5.49nH	0.92pF
4			0.0		4.44nH	0.64pF
5			0.0		3.74nH	0.55pF
6			0.0		3.14nH	0.46pF
7			0.0		2.85nH	0.40pF
8			0.0		2.85nH	0.40pF
9			0.0		3.14nH	0.46pF
10			0.0		3.74nH	0.55pF
11			0.0		4.44nH	0.64pF
12			0.0		5.49nH	0.92pF
13			0.0		6.75nH	0.98pF
14			0.0		8.15nH	1.06pF
15			0.0		8.15nH	1.06pF		
16			0.0		6.75nH	0.98pF		
17			0.0		5.49nH	0.92pF		
18			0.0		4.44nH	0.64pF		
19			0.0		3.74nH	0.55pF		
20			0.0		3.14nH	0.46pF		
21			0.0		2.85nH	0.40pF		
22			0.0		2.85nH	0.40pF		
23			0.0		3.14nH	0.46pF		
24			0.0		3.74nH	0.55pF		
25			0.0		4.44nH	0.64pF		
26			0.0		5.49nH	0.92pF		
27			0.0		6.75nH	0.98pF		
28			0.0		8.15nH	1.06pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP14
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		2.56nH	0.42pF
2			0.0		1.92nH	0.37pF
3			0.0		1.91nH	0.34pF
4			0.0		1.93nH	0.33pF
5			0.0		1.89nH	0.34pF
6			0.0		1.88nH	0.37pF
7			0.0		2.53nH	0.42pF
8			0.0		2.53nH	0.42pF		
9			0.0		1.88nH	0.37pF		
10			0.0		1.89nH	0.34pF		
11			0.0		1.93nH	0.33pF		
12			0.0		1.91nH	0.34pF		
13			0.0		1.92nH	0.37pF		
14			0.0		2.56nH	0.42pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP16
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		5.07nH	0.50pF
2			0.0		3.94nH	0.36pF
3			0.0		3.43nH	0.23pF
4			0.0		2.97nH	0.22pF
5			0.0		2.97nH	0.22pF
6			0.0		3.43nH	0.23pF
7			0.0		3.94nH	0.36pF
8			0.0		5.07nH	0.50pF
9			0.0		5.07nH	0.50pF		
10			0.0		3.94nH	0.36pF		
11			0.0		3.43nH	0.23pF		
12			0.0		2.97nH	0.22pF		
13			0.0		2.97nH	0.22pF		
14			0.0		3.43nH	0.23pF		
15			0.0		3.94nH	0.36pF		
16			0.0		5.07nH	0.50pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP20
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		5.16nH	0.43pF
2			0.0		4.57nH	0.42pF
3			0.0		3.98nH	0.42pF
4			0.0		3.79nH	0.41pF
5			0.0		3.60nH	0.37pF
6			0.0		3.60nH	0.37pF
7			0.0		3.79nH	0.41pF
8			0.0		3.98nH	0.42pF
9			0.0		4.57nH	0.42pF
10			0.0		5.16nH	0.43pF
11			0.0		5.16nH	0.43pF		
12			0.0		4.57nH	0.42pF		
13			0.0		3.98nH	0.42pF		
14			0.0		3.79nH	0.41pF		
15			0.0		3.60nH	0.37pF		
16			0.0		3.60nH	0.37pF		
17			0.0		3.79nH	0.41pF		
18			0.0		3.98nH	0.42pF		
19			0.0		4.57nH	0.42pF		
20			0.0		5.16nH	0.43pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP24
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		5.30nH	0.43pF
2			0.0		4.73nH	0.41pF
3			0.0		4.17nH	0.39pF
4			0.0		3.67nH	0.36pF
5			0.0		3.44nH	0.35pF
6			0.0		3.34nH	0.33pF
7			0.0		3.34nH	0.33pF
8			0.0		3.44nH	0.35pF
9			0.0		3.67nH	0.36pF
10			0.0		4.17nH	0.39pF
11			0.0		4.73nH	0.41pF
12			0.0		5.30nH	0.43pF
13			0.0		5.30nH	0.43pF		
14			0.0		4.73nH	0.41pF		
15			0.0		4.17nH	0.39pF		
16			0.0		3.67nH	0.36pF		
17			0.0		3.44nH	0.35pF		
18			0.0		3.34nH	0.33pF		
19			0.0		3.34nH	0.33pF		
20			0.0		3.44nH	0.35pF		
21			0.0		3.67nH	0.36pF		
22			0.0		4.17nH	0.39pF		
23			0.0		4.73nH	0.41pF		
24			0.0		5.30nH	0.43pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP28
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		5.70nH	0.29pF
2			0.0		4.92nH	0.25pF
3			0.0		4.29nH	0.22pF
4			0.0		3.65nH	0.19pF
5			0.0		3.51nH	0.18pF
6			0.0		3.41nH	0.17pF
7			0.0		3.36nH	0.17pF
8			0.0		3.36nH	0.17pF
9			0.0		3.41nH	0.17pF
10			0.0		3.51nH	0.18pF
11			0.0		3.65nH	0.19pF
12			0.0		4.29nH	0.22pF
13			0.0		4.92nH	0.25pF
14			0.0		5.70nH	0.29pF
15			0.0		5.70nH	0.29pF		
16			0.0		4.92nH	0.25pF		
17			0.0		4.29nH	0.22pF		
18			0.0		3.65nH	0.19pF		
19			0.0		3.51nH	0.18pF		
20			0.0		3.41nH	0.17pF		
21			0.0		3.36nH	0.17pF		
22			0.0		3.36nH	0.17pF		
23			0.0		3.41nH	0.17pF		
24			0.0		3.51nH	0.18pF		
25			0.0		3.65nH	0.19pF		
26			0.0		4.29nH	0.22pF		
27			0.0		4.92nH	0.25pF		
28			0.0		5.70nH	0.29pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP48
Type		SSOP
|
Pin		R_pin		L_pin		C_pin
|
1			0.0		7.22nH	0.74pF
2			0.0		6.48nH	0.71pF
3			0.0		5.80nH	0.69pF
4			0.0		5.17nH	0.59pF
5			0.0		4.52nH	0.48pF
6			0.0		4.32nH	0.45pF
7			0.0		4.10nH	0.41pF
8			0.0		3.87nH	0.38pF
9			0.0		3.67nH	0.35pF
10			0.0		3.50nH	0.32pF
11			0.0		3.39nH	0.30pF
12			0.0		3.29nH	0.28pF
13			0.0		3.29nH	0.28pF
14			0.0		3.39nH	0.30pF
15			0.0		3.50nH	0.32pF
16			0.0		3.67nH	0.35pF
17			0.0		3.87nH	0.38pF
18			0.0		4.10nH	0.41pF
19			0.0		4.32nH	0.45pF
20			0.0		4.52nH	0.48pF
21			0.0		5.17nH	0.59pF
22			0.0		5.80nH	0.69pF
23			0.0		6.48nH	0.71pF
24			0.0		7.22nH	0.74pF
25			0.0		7.22nH	0.74pF		
26			0.0		6.48nH	0.71pF		
27			0.0		5.80nH	0.69pF		
28			0.0		5.17nH	0.59pF		
29			0.0		4.52nH	0.48pF		
30			0.0		4.32nH	0.45pF		
31			0.0		4.10nH	0.41pF		
32			0.0		3.87nH	0.38pF		
33			0.0		3.67nH	0.35pF		
34			0.0		3.50nH	0.32pF		
35			0.0		3.39nH	0.30pF		
36			0.0		3.29nH	0.28pF		
37			0.0		3.29nH	0.28pF		
38			0.0		3.39nH	0.30pF		
39			0.0		3.50nH	0.32pF		
40			0.0		3.67nH	0.35pF		
41			0.0		3.87nH	0.38pF		
42			0.0		4.10nH	0.41pF		
43			0.0		4.32nH	0.45pF		
44			0.0		4.52nH	0.48pF		
45			0.0		5.17nH	0.59pF		
46			0.0		5.80nH	0.69pF		
47			0.0		6.48nH	0.71pF		
48			0.0		7.22nH	0.74pF		
|
|==============================================================================
|==============================================================================
[Package]		SSOP56
Type		SSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		8.62nH		0.80pF
2			0.0		7.76nH		0.77pF
3			0.0		6.96nH		0.74pF
4			0.0		6.25nH		0.71pF
5			0.0		5.43nH		0.69pF
6			0.0		4.71nH		0.59pF
7			0.0		4.39nH		0.48pF
8			0.0		4.12nH		0.45pF
9			0.0		3.81nH		0.41pF
10			0.0		3.57nH		0.38pF
11			0.0		3.40nH		0.35pF
12			0.0		3.23nH		0.32pF
13			0.0		3.13nH		0.30pF
14			0.0		3.07nH		0.28pF
15			0.0		3.07nH		0.28pF
16			0.0		3.13nH		0.30pF
17			0.0		3.23nH		0.32pF
18			0.0		3.40nH		0.35pF
19			0.0		3.57nH		0.38pF
20			0.0		3.81nH		0.41pF
21			0.0		4.12nH		0.45pF
22			0.0		4.39nH		0.48pF
23			0.0		4.71nH		0.59pF
24			0.0		5.43nH		0.69pF
25			0.0		6.25nH		0.71pF
26			0.0		6.96nH		0.74pF
27			0.0		7.76nH		0.77pF
28			0.0		8.62nH		0.80pF
29			0.0		8.62nH		0.80pF		
30			0.0		7.76nH		0.77pF		
31			0.0		6.96nH		0.74pF		
32			0.0		6.25nH		0.71pF		
33			0.0		5.43nH		0.69pF		
34			0.0		4.71nH		0.59pF		
35			0.0		4.39nH		0.48pF		
36			0.0		4.12nH		0.45pF		
37			0.0		3.81nH		0.41pF		
38			0.0		3.57nH		0.38pF		
39			0.0		3.40nH		0.35pF		
40			0.0		3.23nH		0.32pF		
41			0.0		3.13nH		0.30pF		
42			0.0		3.07nH		0.28pF		
43			0.0		3.07nH		0.28pF		
44			0.0		3.13nH		0.30pF		
45			0.0		3.23nH		0.32pF		
46			0.0		3.40nH		0.35pF		
47			0.0		3.57nH		0.38pF		
48			0.0		3.81nH		0.41pF		
49			0.0		4.12nH		0.45pF		
50			0.0		4.39nH		0.48pF		
51			0.0		4.71nH		0.59pF		
52			0.0		5.43nH		0.69pF		
53			0.0		6.25nH		0.71pF		
54			0.0		6.96nH		0.74pF		
55			0.0		7.76nH		0.77pF		
56			0.0		8.62nH		0.80pF		
|
|==============================================================================
|==============================================================================
[Package]		TSSOP14
Type		TSSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		1.66nH		0.19pF
2			0.0		1.30nH		0.18pF
3			0.0		1.29nH		0.16pF
4			0.0		1.28nH		0.16pF
5			0.0		1.32nH		0.16pF
6			0.0		1.31nH		0.18pF
7			0.0		1.71nH		0.19pF
8			0.0		1.71nH		0.19pF		
9			0.0		1.31nH		0.18pF		
10			0.0		1.32nH		0.16pF		
11			0.0		1.28nH		0.16pF		
12			0.0		1.29nH		0.16pF		
13			0.0		1.30nH		0.18pF		
14			0.0		1.66nH		0.19pF		
|
|==============================================================================
|==============================================================================
[Package]		TSSOP20
Type		TSSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		3.65nH		0.27pF
2			0.0		3.02nH		0.26pF
3			0.0		2.22nH		0.24pF
4			0.0		1.88nH		0.23pF
5			0.0		1.65nH		0.21pF
6			0.0		1.65nH		0.21pF
7			0.0		1.88nH		0.23pF
8			0.0		2.22nH		0.24pF
9			0.0		3.02nH		0.26pF
10			0.0		3.65nH		0.27pF
11			0.0		3.65nH		0.27pF		
12			0.0		3.02nH		0.26pF		
13			0.0		2.22nH		0.24pF		
14			0.0		1.88nH		0.23pF		
15			0.0		1.65nH		0.21pF		
16			0.0		1.65nH		0.21pF		
17			0.0		1.88nH		0.23pF		
18			0.0		2.22nH		0.24pF		
19			0.0		3.02nH		0.26pF		
20			0.0		3.65nH		0.27pF		
|
|==============================================================================
|==============================================================================
[Package]		TSSOP24
Type		TSSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		3.29nH		0.37pF
2			0.0		2.76nH		0.34pF
3			0.0		2.24nH		0.30pF
4			0.0		1.73nH		0.29pF
5			0.0		1.50nH		0.28pF
6			0.0		1.38nH		0.27pF
7			0.0		1.38nH		0.27pF
8			0.0		1.50nH		0.28pF
9			0.0		1.73nH		0.29pF
10			0.0		2.24nH		0.30pF
11			0.0		2.76nH		0.34pF
12			0.0		3.29nH		0.37pF
13			0.0		3.29nH		0.37pF		
14			0.0		2.76nH		0.34pF		
15			0.0		2.24nH		0.30pF		
16			0.0		1.73nH		0.29pF		
17			0.0		1.50nH		0.28pF		
18			0.0		1.38nH		0.27pF		
19			0.0		1.38nH		0.27pF		
20			0.0		1.50nH		0.28pF		
21			0.0		1.73nH		0.29pF		
22			0.0		2.24nH		0.30pF		
23			0.0		2.76nH		0.34pF		
24			0.0		3.29nH		0.37pF		
|
|==============================================================================
|==============================================================================
[Package]		TSSOP48
Type		TSSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		5.20nH		0.49pF
2			0.0		4.65nH		0.44pF
3			0.0		4.14nH		0.39pF
4			0.0		3.64nH		0.33pF
5			0.0		3.17nH		0.28pF
6			0.0		2.63nH		0.23pF
7			0.0		2.39nH		0.22pF
8			0.0		2.16nH		0.21pF
9			0.0		2.00nH		0.20pF
10			0.0		1.87nH		0.18pF
11			0.0		1.75nH		0.17pF
12			0.0		1.75nH		0.16pF
13			0.0		1.75nH		0.16pF
14			0.0		1.75nH		0.17pF
15			0.0		1.87nH		0.18pF
16			0.0		2.00nH		0.20pF
17			0.0		2.16nH		0.21pF
18			0.0		2.39nH		0.22pF
19			0.0		2.63nH		0.23pF
20			0.0		3.17nH		0.28pF
21			0.0		3.64nH		0.33pF
22			0.0		4.14nH		0.39pF
23			0.0		4.65nH		0.44pF
24			0.0		5.20nH		0.49pF
25			0.0		5.20nH		0.49pF		
26			0.0		4.65nH		0.44pF		
27			0.0		4.14nH		0.39pF		
28			0.0		3.64nH		0.33pF		
29			0.0		3.17nH		0.28pF		
30			0.0		2.63nH		0.23pF		
31			0.0		2.39nH		0.22pF		
32			0.0		2.16nH		0.21pF		
33			0.0		2.00nH		0.20pF		
34			0.0		1.87nH		0.18pF		
35			0.0		1.75nH		0.17pF		
36			0.0		1.75nH		0.16pF		
37			0.0		1.75nH		0.16pF		
38			0.0		1.75nH		0.17pF		
39			0.0		1.87nH		0.18pF		
40			0.0		2.00nH		0.20pF		
41			0.0		2.16nH		0.21pF		
42			0.0		2.39nH		0.22pF		
43			0.0		2.63nH		0.23pF		
44			0.0		3.17nH		0.28pF		
45			0.0		3.64nH		0.33pF		
46			0.0		4.14nH		0.39pF		
47			0.0		4.65nH		0.44pF		
48			0.0		5.20nH		0.49pF		
|
|==============================================================================
|==============================================================================
[Package]		TSSOP56
Type		TSSOP
|
Pin		R_pin		L_pin			C_pin
|
1			0.0		6.01nH		0.53pF
2			0.0		5.43nH		0.61pF
3			0.0		4.85nH		0.52pF
4			0.0		4.30nH		0.43pF
5			0.0		3.80nH		0.35pF
6			0.0		3.33nH		0.27pF
7			0.0		3.09nH		0.26pF
8			0.0		2.84nH		0.25pF
9			0.0		2.63nH		0.23pF
10			0.0		2.43nH		0.21pF
11			0.0		2.29nH		0.19pF
12			0.0		2.17nH		0.17pF
13			0.0		2.10nH		0.16pF
14			0.0		2.05nH		0.14pF
15			0.0		2.05nH		0.14pF
16			0.0		2.10nH		0.16pF
17			0.0		2.17nH		0.17pF
18			0.0		2.29nH		0.19pF
19			0.0		2.43nH		0.21pF
20			0.0		2.63nH		0.23pF
21			0.0		2.84nH		0.25pF
22			0.0		3.09nH		0.26pF
23			0.0		3.33nH		0.27pF
24			0.0		3.80nH		0.35pF
25			0.0		4.30nH		0.43pF
26			0.0		4.85nH		0.52pF
27			0.0		5.43nH		0.61pF
28			0.0		6.01nH		0.53pF
29			0.0		6.01nH		0.53pF		
30			0.0		5.43nH		0.61pF		
31			0.0		4.85nH		0.52pF		
32			0.0		4.30nH		0.43pF		
33			0.0		3.80nH		0.35pF		
34			0.0		3.33nH		0.27pF		
35			0.0		3.09nH		0.26pF		
36			0.0		2.84nH		0.25pF		
37			0.0		2.63nH		0.23pF		
38			0.0		2.43nH		0.21pF		
39			0.0		2.29nH		0.19pF		
40			0.0		2.17nH		0.17pF		
41			0.0		2.10nH		0.16pF		
42			0.0		2.05nH		0.14pF		
43			0.0		2.05nH		0.14pF		
44			0.0		2.10nH		0.16pF		
45			0.0		2.17nH		0.17pF		
46			0.0		2.29nH		0.19pF		
47			0.0		2.43nH		0.21pF		
48			0.0		2.63nH		0.23pF		
49			0.0		2.84nH		0.25pF		
50			0.0		3.09nH		0.26pF		
51			0.0		3.33nH		0.27pF		
52			0.0		3.80nH		0.35pF		
53			0.0		4.30nH		0.43pF		
54			0.0		4.85nH		0.52pF		
55			0.0		5.43nH		0.61pF		
56			0.0		6.01nH		0.53pF		
|
|==============================================================================
|==============================================================================
| Note:	The [Contents] record and all [Package] records must precede the
|			first [Component] record in the file
|==============================================================================
|==============================================================================
[Component]			74HC00_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC00_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC00_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC00_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC02_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			B4  				74HCXX:GATE			IN
13			Y4  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC02_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			B4  				74HCXX:GATE			IN
13			Y4  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC02_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			B4  				74HCXX:GATE			IN
13			Y4  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC02_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			B4  				74HCXX:GATE			IN
13			Y4  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC03_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y3					74HCXX:OPEN-DRN  	OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC03_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y3					74HCXX:OPEN-DRN  	OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC03_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y3					74HCXX:OPEN-DRN  	OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC03_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y3					74HCXX:OPEN-DRN  	OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC04_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC04_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC04_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC04_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC05_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:OPEN-DRN  	OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y4					74HCXX:OPEN-DRN  	OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:OPEN-DRN  	OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:OPEN-DRN  	OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC05_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:OPEN-DRN  	OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y4					74HCXX:OPEN-DRN  	OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:OPEN-DRN  	OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:OPEN-DRN  	OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC05_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:OPEN-DRN  	OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y4					74HCXX:OPEN-DRN  	OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:OPEN-DRN  	OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:OPEN-DRN  	OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC05_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:OPEN-DRN  	OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:OPEN-DRN  	OUT
7			GND  				GND  					NA
8			Y4					74HCXX:OPEN-DRN  	OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:OPEN-DRN  	OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:OPEN-DRN  	OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC08_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC08_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC08_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC08_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC10_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC10_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC10_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC10_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC11_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC11_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC11_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC11_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC14_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC14_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC14_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC14_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y1					74HCXX:GATE			OUT
3			A2					74HCXX:GATE			IN
4			Y2					74HCXX:GATE			OUT
5			A3					74HCXX:GATE			IN
6			Y3					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y4					74HCXX:GATE			OUT
9			A4					74HCXX:GATE			IN
10			Y5  				74HCXX:GATE			OUT
11			A5  				74HCXX:GATE			IN
12			Y6  				74HCXX:GATE			OUT
13			A6  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC20_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC20_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC20_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC20_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC21_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC21_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC21_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC21_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			NC					NC						NA
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y2					74HCXX:GATE			OUT
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			NC  				NC						NA
12			C2  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC27_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC27_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC27_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC27_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			B2					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			C3  				74HCXX:GATE			IN
12			Y1  				74HCXX:GATE			OUT
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC30_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			GND  				GND  					NA
8			Y 					74HCXX:GATE			OUT
9			NC					NC						NA
10			NC  				NC						NA
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC30_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			GND  				GND  					NA
8			Y 					74HCXX:GATE			OUT
9			NC					NC						NA
10			NC  				NC						NA
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC30_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			GND  				GND  					NA
8			Y 					74HCXX:GATE			OUT
9			NC					NC						NA
10			NC  				NC						NA
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC30_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			GND  				GND  					NA
8			Y 					74HCXX:GATE			OUT
9			NC					NC						NA
10			NC  				NC						NA
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC32_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC32_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC32_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC32_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC36_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC36_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC36_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC36_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC42_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			0 					74HCXX:GATE			OUT
2			1 					74HCXX:GATE			OUT
3			2 					74HCXX:GATE			OUT
4			3 					74HCXX:GATE			OUT
5			4 					74HCXX:GATE			OUT
6			5 					74HCXX:GATE			OUT
7			6 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			7 					74HCXX:GATE			OUT
10			8					74HCXX:GATE			OUT
11			9					74HCXX:GATE			OUT
12			D					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			B					74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC42_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			0 					74HCXX:GATE			OUT
2			1 					74HCXX:GATE			OUT
3			2 					74HCXX:GATE			OUT
4			3 					74HCXX:GATE			OUT
5			4 					74HCXX:GATE			OUT
6			5 					74HCXX:GATE			OUT
7			6 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			7 					74HCXX:GATE			OUT
10			8					74HCXX:GATE			OUT
11			9					74HCXX:GATE			OUT
12			D					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			B					74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC42_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			0 					74HCXX:GATE			OUT
2			1 					74HCXX:GATE			OUT
3			2 					74HCXX:GATE			OUT
4			3 					74HCXX:GATE			OUT
5			4 					74HCXX:GATE			OUT
6			5 					74HCXX:GATE			OUT
7			6 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			7 					74HCXX:GATE			OUT
10			8					74HCXX:GATE			OUT
11			9					74HCXX:GATE			OUT
12			D					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			B					74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			C1					74HCXX:GATE			IN
10			D1  				74HCXX:GATE			IN
11			NC  				NC						NA
12			NC  				NC						NA
13			B1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			C1					74HCXX:GATE			IN
10			D1  				74HCXX:GATE			IN
11			NC  				NC						NA
12			NC  				NC						NA
13			B1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			C1					74HCXX:GATE			IN
10			D1  				74HCXX:GATE			IN
11			NC  				NC						NA
12			NC  				NC						NA
13			B1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC51_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			C1					74HCXX:GATE			IN
10			D1  				74HCXX:GATE			IN
11			NC  				NC						NA
12			NC  				NC						NA
13			B1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC58_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC58_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC58_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC58_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y1					74HCXX:GATE			OUT
9			D1					74HCXX:GATE			IN
10			E1  				74HCXX:GATE			IN
11			F1  				74HCXX:GATE			IN
12			B1  				74HCXX:GATE			IN
13			C1  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC73_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1-  			74HCXX:GATE			IN
3			K1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLK_2				74HCXX:GATE			IN
6			CLR_2-  			74HCXX:GATE			IN
7			J2					74HCXX:GATE			IN
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			K2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1  				74HCXX:GATE			OUT
13			Q1- 				74HCXX:GATE			OUT
14			J1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC73_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1-  			74HCXX:GATE			IN
3			K1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLK_2				74HCXX:GATE			IN
6			CLR_2-  			74HCXX:GATE			IN
7			J2					74HCXX:GATE			IN
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			K2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1  				74HCXX:GATE			OUT
13			Q1- 				74HCXX:GATE			OUT
14			J1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC73_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1-  			74HCXX:GATE			IN
3			K1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLK_2				74HCXX:GATE			IN
6			CLR_2-  			74HCXX:GATE			IN
7			J2					74HCXX:GATE			IN
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			K2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1  				74HCXX:GATE			OUT
13			Q1- 				74HCXX:GATE			OUT
14			J1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC73_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1-  			74HCXX:GATE			IN
3			K1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLK_2				74HCXX:GATE			IN
6			CLR_2-  			74HCXX:GATE			IN
7			J2					74HCXX:GATE			IN
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			K2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1  				74HCXX:GATE			OUT
13			Q1- 				74HCXX:GATE			OUT
14			J1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC74_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			CLK_1				74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			CLK_2  			74HCXX:GATE			IN
12			D2  				74HCXX:GATE			IN
13			CLR_2- 			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC74_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			CLK_1				74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			CLK_2  			74HCXX:GATE			IN
12			D2  				74HCXX:GATE			IN
13			CLR_2- 			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC74_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			CLK_1				74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			CLK_2  			74HCXX:GATE			IN
12			D2  				74HCXX:GATE			IN
13			CLR_2- 			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC74_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			CLK_1				74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			CLK_2  			74HCXX:GATE			IN
12			D2  				74HCXX:GATE			IN
13			CLR_2- 			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC75_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q1					74HCXX:GATE			OUT
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			ENABLE_3->4		74HCXX:GATE			IN
5			VCC  				POWER					NA
6			D3					74HCXX:GATE			IN
7			D4					74HCXX:GATE			IN
8			Q4-  				74HCXX:GATE			OUT
9			Q4					74HCXX:GATE			OUT
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			ENABLE_1->2  	74HCXX:GATE			IN
14			Q2- 				74HCXX:GATE			OUT
15			Q2  				74HCXX:GATE			OUT
16			Q1  				74HCXX:GATE			OUT
|
|==============================================================================
|==============================================================================
[Component]			74HC75_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q1					74HCXX:GATE			OUT
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			ENABLE_3->4		74HCXX:GATE			IN
5			VCC  				POWER					NA
6			D3					74HCXX:GATE			IN
7			D4					74HCXX:GATE			IN
8			Q4-  				74HCXX:GATE			OUT
9			Q4					74HCXX:GATE			OUT
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			ENABLE_1->2  	74HCXX:GATE			IN
14			Q2- 				74HCXX:GATE			OUT
15			Q2  				74HCXX:GATE			OUT
16			Q1  				74HCXX:GATE			OUT
|
|==============================================================================
|==============================================================================
[Component]			74HC75_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q1					74HCXX:GATE			OUT
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			ENABLE_3->4		74HCXX:GATE			IN
5			VCC  				POWER					NA
6			D3					74HCXX:GATE			IN
7			D4					74HCXX:GATE			IN
8			Q4-  				74HCXX:GATE			OUT
9			Q4					74HCXX:GATE			OUT
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			ENABLE_1->2  	74HCXX:GATE			IN
14			Q2- 				74HCXX:GATE			OUT
15			Q2  				74HCXX:GATE			OUT
16			Q1  				74HCXX:GATE			OUT
|
|==============================================================================
|==============================================================================
[Component]			74HC76_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			PRESET_1			74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			J1					74HCXX:GATE			IN
5			VCC  				POWER					NA
6			CLK_2				74HCXX:GATE			IN
7			PRESET_2			74HCXX:GATE			IN
8			CLR_2				74HCXX:GATE			IN
9			J2					74HCXX:GATE			IN
10			Q2- 				74HCXX:GATE			OUT
11			Q2  				74HCXX:GATE			OUT
12			K2  				74HCXX:GATE			IN
13			GND 				GND  					NA
14			Q1- 				74HCXX:GATE			OUT
15			Q1  				74HCXX:GATE			OUT
16			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC76_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			PRESET_1			74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			J1					74HCXX:GATE			IN
5			VCC  				POWER					NA
6			CLK_2				74HCXX:GATE			IN
7			PRESET_2			74HCXX:GATE			IN
8			CLR_2				74HCXX:GATE			IN
9			J2					74HCXX:GATE			IN
10			Q2- 				74HCXX:GATE			OUT
11			Q2  				74HCXX:GATE			OUT
12			K2  				74HCXX:GATE			IN
13			GND 				GND  					NA
14			Q1- 				74HCXX:GATE			OUT
15			Q1  				74HCXX:GATE			OUT
16			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC76_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			PRESET_1			74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			J1					74HCXX:GATE			IN
5			VCC  				POWER					NA
6			CLK_2				74HCXX:GATE			IN
7			PRESET_2			74HCXX:GATE			IN
8			CLR_2				74HCXX:GATE			IN
9			J2					74HCXX:GATE			IN
10			Q2- 				74HCXX:GATE			OUT
11			Q2  				74HCXX:GATE			OUT
12			K2  				74HCXX:GATE			IN
13			GND 				GND  					NA
14			Q1- 				74HCXX:GATE			OUT
15			Q1  				74HCXX:GATE			OUT
16			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC78_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			PRE_1-  			74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLR- 				74HCXX:GATE			IN
6			PRE_2-  			74HCXX:GATE			IN
7			K2					74HCXX:GATE			IN
8			Q2					74HCXX:GATE			OUT
9			Q2-  				74HCXX:GATE			OUT
10			J2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC78_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			PRE_1-  			74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLR- 				74HCXX:GATE			IN
6			PRE_2-  			74HCXX:GATE			IN
7			K2					74HCXX:GATE			IN
8			Q2					74HCXX:GATE			OUT
9			Q2-  				74HCXX:GATE			OUT
10			J2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC78_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			PRE_1-  			74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLR- 				74HCXX:GATE			IN
6			PRE_2-  			74HCXX:GATE			IN
7			K2					74HCXX:GATE			IN
8			Q2					74HCXX:GATE			OUT
9			Q2-  				74HCXX:GATE			OUT
10			J2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC78_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			PRE_1-  			74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			VCC  				POWER					NA
5			CLR- 				74HCXX:GATE			IN
6			PRE_2-  			74HCXX:GATE			IN
7			K2					74HCXX:GATE			IN
8			Q2					74HCXX:GATE			OUT
9			Q2-  				74HCXX:GATE			OUT
10			J2  				74HCXX:GATE			IN
11			GND 				GND  					NA
12			Q1- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			K1  				74HCXX:GATE			IN
|
|==============================================================================
|==============================================================================
[Component]			74HC85_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B3					74HCXX:GATE			IN
2			A<B  				74HCXX:GATE			IN
3			A=B  				74HCXX:GATE			IN
4			A>B  				74HCXX:GATE			IN
5			A>B  				74HCXX:GATE			OUT
6			A=B  				74HCXX:GATE			OUT
7			A<B  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			B0					74HCXX:GATE			IN
10			A0  				74HCXX:GATE			IN
11			B1  				74HCXX:GATE			IN
12			A1  				74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			B2  				74HCXX:GATE			IN
15			A3  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC85_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			B3					74HCXX:GATE			IN
2			A<B  				74HCXX:GATE			IN
3			A=B  				74HCXX:GATE			IN
4			A>B  				74HCXX:GATE			IN
5			A>B  				74HCXX:GATE			OUT
6			A=B  				74HCXX:GATE			OUT
7			A<B  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			B0					74HCXX:GATE			IN
10			A0  				74HCXX:GATE			IN
11			B1  				74HCXX:GATE			IN
12			A1  				74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			B2  				74HCXX:GATE			IN
15			A3  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC85_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B3					74HCXX:GATE			IN
2			A<B  				74HCXX:GATE			IN
3			A=B  				74HCXX:GATE			IN
4			A>B  				74HCXX:GATE			IN
5			A>B  				74HCXX:GATE			OUT
6			A=B  				74HCXX:GATE			OUT
7			A<B  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			B0					74HCXX:GATE			IN
10			A0  				74HCXX:GATE			IN
11			B1  				74HCXX:GATE			IN
12			A1  				74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			B2  				74HCXX:GATE			IN
15			A3  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC86_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC86_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC86_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC86_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC107_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			J1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			K1					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			J2					74HCXX:GATE			IN
9			CLK_2-  			74HCXX:GATE			IN
10			CLR_2  			74HCXX:GATE			IN
11			K2  				74HCXX:GATE			IN
12			CLK_1- 			74HCXX:GATE			IN
13			CLR_1  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC107_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			J1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			K1					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			J2					74HCXX:GATE			IN
9			CLK_2-  			74HCXX:GATE			IN
10			CLR_2  			74HCXX:GATE			IN
11			K2  				74HCXX:GATE			IN
12			CLK_1- 			74HCXX:GATE			IN
13			CLR_1  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC107_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			J1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			K1					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			J2					74HCXX:GATE			IN
9			CLK_2-  			74HCXX:GATE			IN
10			CLR_2  			74HCXX:GATE			IN
11			K2  				74HCXX:GATE			IN
12			CLK_1- 			74HCXX:GATE			IN
13			CLR_1  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC107_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			J1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			K1					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			J2					74HCXX:GATE			IN
9			CLK_2-  			74HCXX:GATE			IN
10			CLR_2  			74HCXX:GATE			IN
11			K2  				74HCXX:GATE			IN
12			CLK_1- 			74HCXX:GATE			IN
13			CLR_1  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC109_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			J1					74HCXX:GATE			IN
3			K1-  				74HCXX:GATE			IN
4			CLK_1				74HCXX:GATE			IN
5			PRESET_1-  		74HCXX:GATE			IN
6			Q1					74HCXX:GATE			OUT
7			Q1-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2-  				74HCXX:GATE			OUT
10			Q2  				74HCXX:GATE			OUT
11			PRESET_2- 		74HCXX:GATE			IN
12			CLK_2  			74HCXX:GATE			IN
13			K2- 				74HCXX:GATE			IN
14			J2  				74HCXX:GATE			IN
15			CLR_2- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC109_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			J1					74HCXX:GATE			IN
3			K1-  				74HCXX:GATE			IN
4			CLK_1				74HCXX:GATE			IN
5			PRESET_1-  		74HCXX:GATE			IN
6			Q1					74HCXX:GATE			OUT
7			Q1-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2-  				74HCXX:GATE			OUT
10			Q2  				74HCXX:GATE			OUT
11			PRESET_2- 		74HCXX:GATE			IN
12			CLK_2  			74HCXX:GATE			IN
13			K2- 				74HCXX:GATE			IN
14			J2  				74HCXX:GATE			IN
15			CLR_2- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC109_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR_1-  			74HCXX:GATE			IN
2			J1					74HCXX:GATE			IN
3			K1-  				74HCXX:GATE			IN
4			CLK_1				74HCXX:GATE			IN
5			PRESET_1-  		74HCXX:GATE			IN
6			Q1					74HCXX:GATE			OUT
7			Q1-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2-  				74HCXX:GATE			OUT
10			Q2  				74HCXX:GATE			OUT
11			PRESET_2- 		74HCXX:GATE			IN
12			CLK_2  			74HCXX:GATE			IN
13			K2- 				74HCXX:GATE			IN
14			J2  				74HCXX:GATE			IN
15			CLR_2- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC112_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			Q2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			CLR_2- 			74HCXX:GATE			IN
15			CLR_1- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC112_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			Q2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			CLR_2- 			74HCXX:GATE			IN
15			CLR_1- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC112_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRESET_1-  		74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			Q2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2					74HCXX:GATE			OUT
10			PRESET_2- 		74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			CLR_2- 			74HCXX:GATE			IN
15			CLR_1- 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC113_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC113_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC113_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC113_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK_2  			74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC114_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC114_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC114_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC114_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			K1					74HCXX:GATE			IN
3			J1					74HCXX:GATE			IN
4			PRE_1-  			74HCXX:GATE			IN
5			Q1					74HCXX:GATE			OUT
6			Q1-  				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2-  				74HCXX:GATE			OUT
9			Q2					74HCXX:GATE			OUT
10			PRE_2- 			74HCXX:GATE			IN
11			J2  				74HCXX:GATE			IN
12			K2  				74HCXX:GATE			IN
13			CLK 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC123_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1-  				74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2-  				74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC123_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1-  				74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2-  				74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC125_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2- 				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3-				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4-				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC125_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2- 				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3-				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4-				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC125_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2- 				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3-				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4-				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC125_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2- 				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3-				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4-				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC126_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2  				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3 				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC126_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2  				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3 				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC126_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2  				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3 				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC126_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			OE2  				74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	ENBO
7			GND  				GND  					NA
8			Y3					74HCXX:LINE-DRV  	ENBO
9			A3					74HCXX:GATE			IN
10			OE3 				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	ENBO
12			A4  				74HCXX:GATE			IN
13			OE4 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC132_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC132_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC132_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC132_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC133_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			G 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			Y 					74HCXX:GATE			OUT
10			H					74HCXX:GATE			IN
11			I					74HCXX:GATE			IN
12			J					74HCXX:GATE			IN
13			K					74HCXX:GATE			IN
14			L					74HCXX:GATE			IN
15			M					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC133_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			G 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			Y 					74HCXX:GATE			OUT
10			H					74HCXX:GATE			IN
11			I					74HCXX:GATE			IN
12			J					74HCXX:GATE			IN
13			K					74HCXX:GATE			IN
14			L					74HCXX:GATE			IN
15			M					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC133_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			D 					74HCXX:GATE			IN
5			E 					74HCXX:GATE			IN
6			F 					74HCXX:GATE			IN
7			G 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			Y 					74HCXX:GATE			OUT
10			H					74HCXX:GATE			IN
11			I					74HCXX:GATE			IN
12			J					74HCXX:GATE			IN
13			K					74HCXX:GATE			IN
14			L					74HCXX:GATE			IN
15			M					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC137_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC137_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC137_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC138_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			G2A- 				74HCXX:GATE			IN
5			G2B- 				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6-  				74HCXX:GATE			OUT
10			Y5- 				74HCXX:GATE			OUT
11			Y4- 				74HCXX:GATE			OUT
12			Y3- 				74HCXX:GATE			OUT
13			Y2- 				74HCXX:GATE			OUT
14			Y1- 				74HCXX:GATE			OUT
15			Y0- 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC138_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			G2A- 				74HCXX:GATE			IN
5			G2B- 				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6-  				74HCXX:GATE			OUT
10			Y5- 				74HCXX:GATE			OUT
11			Y4- 				74HCXX:GATE			OUT
12			Y3- 				74HCXX:GATE			OUT
13			Y2- 				74HCXX:GATE			OUT
14			Y1- 				74HCXX:GATE			OUT
15			Y0- 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC138_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			G2A- 				74HCXX:GATE			IN
5			G2B- 				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6-  				74HCXX:GATE			OUT
10			Y5- 				74HCXX:GATE			OUT
11			Y4- 				74HCXX:GATE			OUT
12			Y3- 				74HCXX:GATE			OUT
13			Y2- 				74HCXX:GATE			OUT
14			Y1- 				74HCXX:GATE			OUT
15			Y0- 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC139_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			1Y0  				74HCXX:GATE			OUT
5			1Y1  				74HCXX:GATE			OUT
6			1Y2  				74HCXX:GATE			OUT
7			1Y3  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			2Y3  				74HCXX:GATE			OUT
10			2Y2 				74HCXX:GATE			OUT
11			2Y1 				74HCXX:GATE			OUT
12			2Y0 				74HCXX:GATE			OUT
13			B2  				74HCXX:GATE			IN
14			A2  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC139_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			1Y0  				74HCXX:GATE			OUT
5			1Y1  				74HCXX:GATE			OUT
6			1Y2  				74HCXX:GATE			OUT
7			1Y3  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			2Y3  				74HCXX:GATE			OUT
10			2Y2 				74HCXX:GATE			OUT
11			2Y1 				74HCXX:GATE			OUT
12			2Y0 				74HCXX:GATE			OUT
13			B2  				74HCXX:GATE			IN
14			A2  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC147_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			4 					74HCXX:GATE			IN
2			5 					74HCXX:GATE			IN
3			6 					74HCXX:GATE			IN
4			7 					74HCXX:GATE			IN
5			8 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			OUT
7			B 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			A 					74HCXX:GATE			OUT
10			9					74HCXX:GATE			IN
11			1					74HCXX:GATE			IN
12			2					74HCXX:GATE			IN
13			3					74HCXX:GATE			IN
14			D					74HCXX:GATE			OUT
15			NC  				NC						NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC147_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			4 					74HCXX:GATE			IN
2			5 					74HCXX:GATE			IN
3			6 					74HCXX:GATE			IN
4			7 					74HCXX:GATE			IN
5			8 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			OUT
7			B 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			A 					74HCXX:GATE			OUT
10			9					74HCXX:GATE			IN
11			1					74HCXX:GATE			IN
12			2					74HCXX:GATE			IN
13			3					74HCXX:GATE			IN
14			D					74HCXX:GATE			OUT
15			NC  				NC						NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC148_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			4 					74HCXX:GATE			IN
2			5 					74HCXX:GATE			IN
3			6 					74HCXX:GATE			IN
4			7 					74HCXX:GATE			IN
5			E1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			OUT
7			A1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			A0					74HCXX:GATE			OUT
10			0					74HCXX:GATE			IN
11			1					74HCXX:GATE			IN
12			2					74HCXX:GATE			IN
13			3					74HCXX:GATE			IN
14			GS  				74HCXX:GATE			OUT
15			EO  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC148_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			4 					74HCXX:GATE			IN
2			5 					74HCXX:GATE			IN
3			6 					74HCXX:GATE			IN
4			7 					74HCXX:GATE			IN
5			E1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			OUT
7			A1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			A0					74HCXX:GATE			OUT
10			0					74HCXX:GATE			IN
11			1					74HCXX:GATE			IN
12			2					74HCXX:GATE			IN
13			3					74HCXX:GATE			IN
14			GS  				74HCXX:GATE			OUT
15			EO  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC151_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			OUT
6			W 					74HCXX:GATE			OUT
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC151_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			OUT
6			W 					74HCXX:GATE			OUT
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC151_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			OUT
6			W 					74HCXX:GATE			OUT
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC152_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			D4					74HCXX:GATE			IN
2			D3					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			D0					74HCXX:GATE			IN
6			W 					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			D7  				74HCXX:GATE			IN
12			D6  				74HCXX:GATE			IN
13			D5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC152_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			D4					74HCXX:GATE			IN
2			D3					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			D0					74HCXX:GATE			IN
6			W 					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			D7  				74HCXX:GATE			IN
12			D6  				74HCXX:GATE			IN
13			D5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC152_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			D4					74HCXX:GATE			IN
2			D3					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			D0					74HCXX:GATE			IN
6			W 					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			D7  				74HCXX:GATE			IN
12			D6  				74HCXX:GATE			IN
13			D5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC152_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			D4					74HCXX:GATE			IN
2			D3					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			D0					74HCXX:GATE			IN
6			W 					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			D7  				74HCXX:GATE			IN
12			D6  				74HCXX:GATE			IN
13			D5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC153_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE(G1-)		74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			STROBE(G2-)  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC153_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE(G1-)		74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			STROBE(G2-)  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC153_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE(G1-)		74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			STROBE(G2-)  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC154_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y2					74HCXX:GATE			OUT
3			Y3					74HCXX:GATE			OUT
4			Y4					74HCXX:GATE			OUT
5			Y5					74HCXX:GATE			OUT
6			Y6					74HCXX:GATE			OUT
7			Y7					74HCXX:GATE			OUT
8			Y8					74HCXX:GATE			OUT
9			Y9					74HCXX:GATE			OUT
10			Y10 				74HCXX:GATE			OUT
11			Y11 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y12 				74HCXX:GATE			OUT
14			Y13 				74HCXX:GATE			OUT
15			Y14 				74HCXX:GATE			OUT
16			Y15 				74HCXX:GATE			OUT
17			Y16 				74HCXX:GATE			OUT
18			E0- 				74HCXX:GATE			IN
19			E1- 				74HCXX:GATE			IN
20			A4  				74HCXX:GATE			IN
21			A3  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC154_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y2					74HCXX:GATE			OUT
3			Y3					74HCXX:GATE			OUT
4			Y4					74HCXX:GATE			OUT
5			Y5					74HCXX:GATE			OUT
6			Y6					74HCXX:GATE			OUT
7			Y7					74HCXX:GATE			OUT
8			Y8					74HCXX:GATE			OUT
9			Y9					74HCXX:GATE			OUT
10			Y10 				74HCXX:GATE			OUT
11			Y11 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y12 				74HCXX:GATE			OUT
14			Y13 				74HCXX:GATE			OUT
15			Y14 				74HCXX:GATE			OUT
16			Y15 				74HCXX:GATE			OUT
17			Y16 				74HCXX:GATE			OUT
18			E0- 				74HCXX:GATE			IN
19			E1- 				74HCXX:GATE			IN
20			A4  				74HCXX:GATE			IN
21			A3  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC154_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y2					74HCXX:GATE			OUT
3			Y3					74HCXX:GATE			OUT
4			Y4					74HCXX:GATE			OUT
5			Y5					74HCXX:GATE			OUT
6			Y6					74HCXX:GATE			OUT
7			Y7					74HCXX:GATE			OUT
8			Y8					74HCXX:GATE			OUT
9			Y9					74HCXX:GATE			OUT
10			Y10 				74HCXX:GATE			OUT
11			Y11 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y12 				74HCXX:GATE			OUT
14			Y13 				74HCXX:GATE			OUT
15			Y14 				74HCXX:GATE			OUT
16			Y15 				74HCXX:GATE			OUT
17			Y16 				74HCXX:GATE			OUT
18			E0- 				74HCXX:GATE			IN
19			E1- 				74HCXX:GATE			IN
20			A4  				74HCXX:GATE			IN
21			A3  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC154_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y2					74HCXX:GATE			OUT
3			Y3					74HCXX:GATE			OUT
4			Y4					74HCXX:GATE			OUT
5			Y5					74HCXX:GATE			OUT
6			Y6					74HCXX:GATE			OUT
7			Y7					74HCXX:GATE			OUT
8			Y8					74HCXX:GATE			OUT
9			Y9					74HCXX:GATE			OUT
10			Y10 				74HCXX:GATE			OUT
11			Y11 				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y12 				74HCXX:GATE			OUT
14			Y13 				74HCXX:GATE			OUT
15			Y14 				74HCXX:GATE			OUT
16			Y15 				74HCXX:GATE			OUT
17			Y16 				74HCXX:GATE			OUT
18			E0- 				74HCXX:GATE			IN
19			E1- 				74HCXX:GATE			IN
20			A4  				74HCXX:GATE			IN
21			A3  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC157_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3					74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4  				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC157_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3					74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4  				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC157_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3					74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4  				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC158_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC158_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC158_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			OUT
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			OUT
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			STROBE(G-)		74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC160_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC160_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC160_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC161_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC161_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC161_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC162_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLEAR-  			74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC162_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLEAR-  			74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC162_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLEAR-  			74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC163_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLEAR-  			74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC163_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLEAR-  			74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P			74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T  		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY 		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC164_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			QA					74HCXX:GATE			OUT
4			QB					74HCXX:GATE			OUT
5			QC					74HCXX:GATE			OUT
6			QD					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			CLK  				74HCXX:GATE			IN
9			CLR  				74HCXX:GATE			IN
10			QE  				74HCXX:GATE			OUT
11			QF  				74HCXX:GATE			OUT
12			QG  				74HCXX:GATE			OUT
13			QH  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC164_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			QA					74HCXX:GATE			OUT
4			QB					74HCXX:GATE			OUT
5			QC					74HCXX:GATE			OUT
6			QD					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			CLK  				74HCXX:GATE			IN
9			CLR  				74HCXX:GATE			IN
10			QE  				74HCXX:GATE			OUT
11			QF  				74HCXX:GATE			OUT
12			QG  				74HCXX:GATE			OUT
13			QH  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC164_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			QA					74HCXX:GATE			OUT
4			QB					74HCXX:GATE			OUT
5			QC					74HCXX:GATE			OUT
6			QD					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			CLK  				74HCXX:GATE			IN
9			CLR  				74HCXX:GATE			IN
10			QE  				74HCXX:GATE			OUT
11			QF  				74HCXX:GATE			OUT
12			QG  				74HCXX:GATE			OUT
13			QH  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC164_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			QA					74HCXX:GATE			OUT
4			QB					74HCXX:GATE			OUT
5			QC					74HCXX:GATE			OUT
6			QD					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			CLK  				74HCXX:GATE			IN
9			CLR  				74HCXX:GATE			IN
10			QE  				74HCXX:GATE			OUT
11			QF  				74HCXX:GATE			OUT
12			QG  				74HCXX:GATE			OUT
13			QH  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC165_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SHIFT/LOAD 		74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			E 					74HCXX:GATE			IN
4			F 					74HCXX:GATE			IN
5			G 					74HCXX:GATE			IN
6			H 					74HCXX:GATE			IN
7			QH-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			QH					74HCXX:GATE			OUT
10			SERIAL_IN 		74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			B					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			D					74HCXX:GATE			IN
15			CLK_INHIBIT  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC165_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			SHIFT/LOAD 		74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			E 					74HCXX:GATE			IN
4			F 					74HCXX:GATE			IN
5			G 					74HCXX:GATE			IN
6			H 					74HCXX:GATE			IN
7			QH-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			QH					74HCXX:GATE			OUT
10			SERIAL_IN 		74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			B					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			D					74HCXX:GATE			IN
15			CLK_INHIBIT  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC165_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SHIFT/LOAD 		74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			E 					74HCXX:GATE			IN
4			F 					74HCXX:GATE			IN
5			G 					74HCXX:GATE			IN
6			H 					74HCXX:GATE			IN
7			QH-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			QH					74HCXX:GATE			OUT
10			SERIAL_IN 		74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			B					74HCXX:GATE			IN
13			C					74HCXX:GATE			IN
14			D					74HCXX:GATE			IN
15			CLK_INHIBIT  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC166_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SERIAL_IN  		74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			CLK_INHIBIT		74HCXX:GATE			IN
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			CLR- 				74HCXX:GATE			IN
10			E					74HCXX:GATE			IN
11			F					74HCXX:GATE			IN
12			G					74HCXX:GATE			IN
13			QH  				74HCXX:GATE			OUT
14			H					74HCXX:GATE			IN
15			SHIFT/LOAD-  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC166_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			SERIAL_IN  		74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			CLK_INHIBIT		74HCXX:GATE			IN
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			CLR- 				74HCXX:GATE			IN
10			E					74HCXX:GATE			IN
11			F					74HCXX:GATE			IN
12			G					74HCXX:GATE			IN
13			QH  				74HCXX:GATE			OUT
14			H					74HCXX:GATE			IN
15			SHIFT/LOAD-  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC166_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SERIAL_IN  		74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			CLK_INHIBIT		74HCXX:GATE			IN
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			CLR- 				74HCXX:GATE			IN
10			E					74HCXX:GATE			IN
11			F					74HCXX:GATE			IN
12			G					74HCXX:GATE			IN
13			QH  				74HCXX:GATE			OUT
14			H					74HCXX:GATE			IN
15			SHIFT/LOAD-  	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC169_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			U/D- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P-  		74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T- 		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY-		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC169_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			U/D- 				74HCXX:GATE			IN
2			CLK  				74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			ENABLE_P-  		74HCXX:GATE			IN
8			GND  				GND  					NA
9			LOAD-				74HCXX:GATE			IN
10			ENABLE_T- 		74HCXX:GATE			IN
11			QD  				74HCXX:GATE			OUT
12			QC  				74HCXX:GATE			OUT
13			QB  				74HCXX:GATE			OUT
14			QA  				74HCXX:GATE			OUT
15			RIP_CARRY-		74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC173_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			M 					74HCXX:GATE			IN
2			N 					74HCXX:GATE			IN
3			Q1					74HCXX:GATE			ENBO
4			Q2					74HCXX:GATE			ENBO
5			Q3					74HCXX:GATE			ENBO
6			Q4					74HCXX:GATE			ENBO
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			G1					74HCXX:GATE			IN
10			G2  				74HCXX:GATE			IN
11			D4  				74HCXX:GATE			IN
12			D3  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			D1  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC173_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			M 					74HCXX:GATE			IN
2			N 					74HCXX:GATE			IN
3			Q1					74HCXX:GATE			ENBO
4			Q2					74HCXX:GATE			ENBO
5			Q3					74HCXX:GATE			ENBO
6			Q4					74HCXX:GATE			ENBO
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			G1					74HCXX:GATE			IN
10			G2  				74HCXX:GATE			IN
11			D4  				74HCXX:GATE			IN
12			D3  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			D1  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC173_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			M 					74HCXX:GATE			IN
2			N 					74HCXX:GATE			IN
3			Q1					74HCXX:GATE			ENBO
4			Q2					74HCXX:GATE			ENBO
5			Q3					74HCXX:GATE			ENBO
6			Q4					74HCXX:GATE			ENBO
7			CLK  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			G1					74HCXX:GATE			IN
10			G2  				74HCXX:GATE			IN
11			D4  				74HCXX:GATE			IN
12			D3  				74HCXX:GATE			IN
13			D2  				74HCXX:GATE			IN
14			D1  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC174_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC174_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC174_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC175_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC175_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC175_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC180_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			EVEN_IN 			74HCXX:GATE			IN
4			ODD_IN  			74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC180_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			EVEN_IN 			74HCXX:GATE			IN
4			ODD_IN  			74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC180_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			EVEN_IN 			74HCXX:GATE			IN
4			ODD_IN  			74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC180_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			EVEN_IN 			74HCXX:GATE			IN
4			ODD_IN  			74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC181_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			B0					74HCXX:GATE			IN
2			A0					74HCXX:GATE			IN
3			S3					74HCXX:GATE			IN
4			S2					74HCXX:GATE			IN
5			S1					74HCXX:GATE			IN
6			S0					74HCXX:GATE			IN
7			Cn					74HCXX:GATE			IN
8			M 					74HCXX:GATE			IN
9			F0					74HCXX:GATE			OUT
10			F1  				74HCXX:GATE			OUT
11			F2  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			F3  				74HCXX:GATE			OUT
14			A=B 				74HCXX:GATE			OUT
15			P					74HCXX:GATE			OUT
16			C(n+4) 			74HCXX:GATE			OUT
17			G					74HCXX:GATE			OUT
18			B3  				74HCXX:GATE			IN
19			A3  				74HCXX:GATE			IN
20			B2  				74HCXX:GATE			IN
21			A2  				74HCXX:GATE			IN
22			B1  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC181_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			B0					74HCXX:GATE			IN
2			A0					74HCXX:GATE			IN
3			S3					74HCXX:GATE			IN
4			S2					74HCXX:GATE			IN
5			S1					74HCXX:GATE			IN
6			S0					74HCXX:GATE			IN
7			Cn					74HCXX:GATE			IN
8			M 					74HCXX:GATE			IN
9			F0					74HCXX:GATE			OUT
10			F1  				74HCXX:GATE			OUT
11			F2  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			F3  				74HCXX:GATE			OUT
14			A=B 				74HCXX:GATE			OUT
15			P					74HCXX:GATE			OUT
16			C(n+4) 			74HCXX:GATE			OUT
17			G					74HCXX:GATE			OUT
18			B3  				74HCXX:GATE			IN
19			A3  				74HCXX:GATE			IN
20			B2  				74HCXX:GATE			IN
21			A2  				74HCXX:GATE			IN
22			B1  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC181_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			B0					74HCXX:GATE			IN
2			A0					74HCXX:GATE			IN
3			S3					74HCXX:GATE			IN
4			S2					74HCXX:GATE			IN
5			S1					74HCXX:GATE			IN
6			S0					74HCXX:GATE			IN
7			Cn					74HCXX:GATE			IN
8			M 					74HCXX:GATE			IN
9			F0					74HCXX:GATE			OUT
10			F1  				74HCXX:GATE			OUT
11			F2  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			F3  				74HCXX:GATE			OUT
14			A=B 				74HCXX:GATE			OUT
15			P					74HCXX:GATE			OUT
16			C(n+4) 			74HCXX:GATE			OUT
17			G					74HCXX:GATE			OUT
18			B3  				74HCXX:GATE			IN
19			A3  				74HCXX:GATE			IN
20			B2  				74HCXX:GATE			IN
21			A2  				74HCXX:GATE			IN
22			B1  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC181_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			B0					74HCXX:GATE			IN
2			A0					74HCXX:GATE			IN
3			S3					74HCXX:GATE			IN
4			S2					74HCXX:GATE			IN
5			S1					74HCXX:GATE			IN
6			S0					74HCXX:GATE			IN
7			Cn					74HCXX:GATE			IN
8			M 					74HCXX:GATE			IN
9			F0					74HCXX:GATE			OUT
10			F1  				74HCXX:GATE			OUT
11			F2  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			F3  				74HCXX:GATE			OUT
14			A=B 				74HCXX:GATE			OUT
15			P					74HCXX:GATE			OUT
16			C(n+4) 			74HCXX:GATE			OUT
17			G					74HCXX:GATE			OUT
18			B3  				74HCXX:GATE			IN
19			A3  				74HCXX:GATE			IN
20			B2  				74HCXX:GATE			IN
21			A2  				74HCXX:GATE			IN
22			B1  				74HCXX:GATE			IN
23			A1  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC182_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			P1-  				74HCXX:GATE			IN
3			G0-  				74HCXX:GATE			IN
4			P0-  				74HCXX:GATE			IN
5			G3-  				74HCXX:GATE			IN
6			P3-  				74HCXX:GATE			IN
7			P-					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			C(n+z)  			74HCXX:GATE			OUT
10			G-  				74HCXX:GATE			OUT
11			C(n+y) 			74HCXX:GATE			OUT
12			C(n+x) 			74HCXX:GATE			OUT
13			Cn  				74HCXX:GATE			IN
14			G2- 				74HCXX:GATE			IN
15			P2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC182_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			P1-  				74HCXX:GATE			IN
3			G0-  				74HCXX:GATE			IN
4			P0-  				74HCXX:GATE			IN
5			G3-  				74HCXX:GATE			IN
6			P3-  				74HCXX:GATE			IN
7			P-					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			C(n+z)  			74HCXX:GATE			OUT
10			G-  				74HCXX:GATE			OUT
11			C(n+y) 			74HCXX:GATE			OUT
12			C(n+x) 			74HCXX:GATE			OUT
13			Cn  				74HCXX:GATE			IN
14			G2- 				74HCXX:GATE			IN
15			P2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC190_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD-  			74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK-  		74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC190_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD-  			74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK-  		74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC190_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD-  			74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK-  		74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC191_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			OB					74HCXX:GATE			OUT
3			OA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			OC					74HCXX:GATE			OUT
7			OD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC191_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			OB					74HCXX:GATE			OUT
3			OA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			OC					74HCXX:GATE			OUT
7			OD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC191_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			OB					74HCXX:GATE			OUT
3			OA					74HCXX:GATE			OUT
4			ENABLE_G			74HCXX:GATE			IN
5			DOWN/UP-			74HCXX:GATE			IN
6			OC					74HCXX:GATE			OUT
7			OD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			MAX/MIN			74HCXX:GATE			OUT
13			RIP_CLK			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC192_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC192_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC192_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC193_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC193_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC193_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			DATA_B  			74HCXX:GATE			IN
2			QB					74HCXX:GATE			OUT
3			QA					74HCXX:GATE			OUT
4			COUNT_DOWN 		74HCXX:GATE			IN
5			COUNT_UP			74HCXX:GATE			IN
6			QC					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			DATA_D  			74HCXX:GATE			IN
10			DATA_C 			74HCXX:GATE			IN
11			LOAD				74HCXX:GATE			IN
12			CARRY  			74HCXX:GATE			OUT
13			BORROW 			74HCXX:GATE			OUT
14			CLR 				74HCXX:GATE			IN
15			DATA_A 			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC194_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			SHIFT_RT			74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			SHIFT_LEFT 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			S0					74HCXX:GATE			IN
10			S1  				74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC194_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			SHIFT_RT			74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			SHIFT_LEFT 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			S0					74HCXX:GATE			IN
10			S1  				74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC194_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			SHIFT_RT			74HCXX:GATE			IN
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			IN
5			C 					74HCXX:GATE			IN
6			D 					74HCXX:GATE			IN
7			SHIFT_LEFT 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			S0					74HCXX:GATE			IN
10			S1  				74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC195_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			J 					74HCXX:GATE			IN
3			K-					74HCXX:GATE			IN
4			A 					74HCXX:GATE			IN
5			B 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			IN
7			D 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			SHIFT/LOAD 		74HCXX:GATE			IN
10			CLK 				74HCXX:GATE			IN
11			QD- 				74HCXX:GATE			OUT
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC195_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			J 					74HCXX:GATE			IN
3			K-					74HCXX:GATE			IN
4			A 					74HCXX:GATE			IN
5			B 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			IN
7			D 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			SHIFT/LOAD 		74HCXX:GATE			IN
10			CLK 				74HCXX:GATE			IN
11			QD- 				74HCXX:GATE			OUT
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC195_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR  				74HCXX:GATE			IN
2			J 					74HCXX:GATE			IN
3			K-					74HCXX:GATE			IN
4			A 					74HCXX:GATE			IN
5			B 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			IN
7			D 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			SHIFT/LOAD 		74HCXX:GATE			IN
10			CLK 				74HCXX:GATE			IN
11			QD- 				74HCXX:GATE			OUT
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC221_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			OUT
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC221_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			OUT
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC237_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC237_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC237_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A 					74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			C 					74HCXX:GATE			IN
4			GL-  				74HCXX:GATE			IN
5			G2-  				74HCXX:GATE			IN
6			G1					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC238_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A0					74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			E1-  				74HCXX:GATE			IN
5			E2-  				74HCXX:GATE			IN
6			E3					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC238_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A0					74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			E1-  				74HCXX:GATE			IN
5			E2-  				74HCXX:GATE			IN
6			E3					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC238_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A0					74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			E1-  				74HCXX:GATE			IN
5			E2-  				74HCXX:GATE			IN
6			E3					74HCXX:GATE			IN
7			Y7					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y6					74HCXX:GATE			OUT
10			Y5  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			Y3  				74HCXX:GATE			OUT
13			Y2  				74HCXX:GATE			OUT
14			Y1  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC239_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			1Y0  				74HCXX:GATE			OUT
5			1Y1  				74HCXX:GATE			OUT
6			1Y2  				74HCXX:GATE			OUT
7			1Y3  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			2Y3  				74HCXX:GATE			OUT
10			2Y2 				74HCXX:GATE			OUT
11			2Y1 				74HCXX:GATE			OUT
12			2Y0 				74HCXX:GATE			OUT
13			B2  				74HCXX:GATE			IN
14			A2  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC239_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			1Y0  				74HCXX:GATE			OUT
5			1Y1  				74HCXX:GATE			OUT
6			1Y2  				74HCXX:GATE			OUT
7			1Y3  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			2Y3  				74HCXX:GATE			OUT
10			2Y2 				74HCXX:GATE			OUT
11			2Y1 				74HCXX:GATE			OUT
12			2Y0 				74HCXX:GATE			OUT
13			B2  				74HCXX:GATE			IN
14			A2  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC239_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			1Y0  				74HCXX:GATE			OUT
5			1Y1  				74HCXX:GATE			OUT
6			1Y2  				74HCXX:GATE			OUT
7			1Y3  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			2Y3  				74HCXX:GATE			OUT
10			2Y2 				74HCXX:GATE			OUT
11			2Y1 				74HCXX:GATE			OUT
12			2Y0 				74HCXX:GATE			OUT
13			B2  				74HCXX:GATE			IN
14			A2  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC240_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC240_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC240_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC240_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC241_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC241_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC241_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC241_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC242_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC242_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC242_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC242_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC243_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC243_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC243_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC243_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB- 				74HCXX:GATE			IN
2			NC					NC						NA
3			A1					74HCXX:LINE-DRV  	BIDIR
4			A2					74HCXX:LINE-DRV  	BIDIR
5			A3					74HCXX:LINE-DRV  	BIDIR
6			A4					74HCXX:LINE-DRV  	BIDIR
7			GND  				GND  					NA
8			B4					74HCXX:LINE-DRV  	BIDIR
9			B3					74HCXX:LINE-DRV  	BIDIR
10			B2  				74HCXX:LINE-DRV  	BIDIR
11			B1  				74HCXX:LINE-DRV  	BIDIR
12			NC  				NC						NA
13			GBA 				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC244_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC244_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC244_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC244_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			2Y4  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			2Y3  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			2Y2  				74HCXX:LINE-DRV  	ENBO
8			1A4  				74HCXX:GATE			IN
9			2Y1  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			2A1 				74HCXX:GATE			IN
12			1Y4 				74HCXX:LINE-DRV  	ENBO
13			2A2 				74HCXX:GATE			IN
14			1Y3 				74HCXX:LINE-DRV  	ENBO
15			2A3 				74HCXX:GATE			IN
16			1Y2 				74HCXX:LINE-DRV  	ENBO
17			2A4 				74HCXX:GATE			IN
18			1Y1 				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC245_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			T/R- 				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			OE- 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC245_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			T/R- 				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			OE- 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC245_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			T/R- 				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			OE- 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC245_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			T/R- 				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			OE- 				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC251_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			ENBO
6			W 					74HCXX:GATE			ENBO
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC251_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			ENBO
6			W 					74HCXX:GATE			ENBO
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC251_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D3					74HCXX:GATE			IN
2			D2					74HCXX:GATE			IN
3			D1					74HCXX:GATE			IN
4			D0					74HCXX:GATE			IN
5			Y 					74HCXX:GATE			ENBO
6			W 					74HCXX:GATE			ENBO
7			STROBE(G-) 		74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			D7  				74HCXX:GATE			IN
13			D6  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC253_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC253_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC253_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC257_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1					74HCXX:GATE			ENBO
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y3					74HCXX:GATE			ENBO
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4  				74HCXX:GATE			ENBO
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			OUT_CTRL(G-) 	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC257_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1					74HCXX:GATE			ENBO
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y3					74HCXX:GATE			ENBO
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4  				74HCXX:GATE			ENBO
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			OUT_CTRL(G-) 	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC258_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			ENBO
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			ENBO
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			ENBO
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			OUT_CTRL(G-) 	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC258_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			ENBO
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			ENBO
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			ENBO
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			OUT_CTRL(G-) 	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC258_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			SELECT(A-/B)  	74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			B1					74HCXX:GATE			IN
4			Y1-  				74HCXX:GATE			ENBO
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			Y2-  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y3-  				74HCXX:GATE			ENBO
10			B3  				74HCXX:GATE			IN
11			A3  				74HCXX:GATE			IN
12			Y4- 				74HCXX:GATE			ENBO
13			B4  				74HCXX:GATE			IN
14			A4  				74HCXX:GATE			IN
15			OUT_CTRL(G-) 	74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC259_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC259_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC259_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC260_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			NC					NC						NA
4			I 					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC260_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			NC					NC						NA
4			I 					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC260_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			NC					NC						NA
4			I 					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC260_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			G 					74HCXX:GATE			IN
2			H 					74HCXX:GATE			IN
3			NC					NC						NA
4			I 					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			A 					74HCXX:GATE			IN
9			B 					74HCXX:GATE			IN
10			C					74HCXX:GATE			IN
11			D					74HCXX:GATE			IN
12			E					74HCXX:GATE			IN
13			F					74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-COL  	OUT
4			Y2					74HCXX:OPEN-COL  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-COL  	OUT
11			Y4  				74HCXX:OPEN-COL  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-COL  	OUT
4			Y2					74HCXX:OPEN-COL  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-COL  	OUT
11			Y4  				74HCXX:OPEN-COL  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-COL  	OUT
4			Y2					74HCXX:OPEN-COL  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-COL  	OUT
11			Y4  				74HCXX:OPEN-COL  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-COL  	OUT
4			Y2					74HCXX:OPEN-COL  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-COL  	OUT
11			Y4  				74HCXX:OPEN-COL  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-DRN  	OUT
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-DRN  	OUT
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-DRN  	OUT
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC266_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:OPEN-DRN  	OUT
4			Y2					74HCXX:OPEN-DRN  	OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:OPEN-DRN  	OUT
11			Y4  				74HCXX:OPEN-DRN  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC273_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC273_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC273_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC273_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CLR- 				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC280_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			I6					74HCXX:GATE			IN
2			I7					74HCXX:GATE			IN
3			NC					NC						NA
4			I8					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			I0					74HCXX:GATE			IN
9			I1					74HCXX:GATE			IN
10			I2  				74HCXX:GATE			IN
11			I3  				74HCXX:GATE			IN
12			I4  				74HCXX:GATE			IN
13			I5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC280_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			I6					74HCXX:GATE			IN
2			I7					74HCXX:GATE			IN
3			NC					NC						NA
4			I8					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			I0					74HCXX:GATE			IN
9			I1					74HCXX:GATE			IN
10			I2  				74HCXX:GATE			IN
11			I3  				74HCXX:GATE			IN
12			I4  				74HCXX:GATE			IN
13			I5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC280_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			I6					74HCXX:GATE			IN
2			I7					74HCXX:GATE			IN
3			NC					NC						NA
4			I8					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			I0					74HCXX:GATE			IN
9			I1					74HCXX:GATE			IN
10			I2  				74HCXX:GATE			IN
11			I3  				74HCXX:GATE			IN
12			I4  				74HCXX:GATE			IN
13			I5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC280_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			I6					74HCXX:GATE			IN
2			I7					74HCXX:GATE			IN
3			NC					NC						NA
4			I8					74HCXX:GATE			IN
5			SUM_EVEN			74HCXX:GATE			OUT
6			SUM_ODD 			74HCXX:GATE			OUT
7			GND  				GND  					NA
8			I0					74HCXX:GATE			IN
9			I1					74HCXX:GATE			IN
10			I2  				74HCXX:GATE			IN
11			I3  				74HCXX:GATE			IN
12			I4  				74HCXX:GATE			IN
13			I5  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC283_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S1					74HCXX:GATE			OUT
2			B1					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			S0					74HCXX:GATE			OUT
5			A0					74HCXX:GATE			IN
6			B0					74HCXX:GATE			IN
7			Cin  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			Cout 				74HCXX:GATE			OUT
10			S3  				74HCXX:GATE			OUT
11			B3  				74HCXX:GATE			IN
12			A3  				74HCXX:GATE			IN
13			S2  				74HCXX:GATE			OUT
14			A2  				74HCXX:GATE			IN
15			B2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC283_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			S1					74HCXX:GATE			OUT
2			B1					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			S0					74HCXX:GATE			OUT
5			A0					74HCXX:GATE			IN
6			B0					74HCXX:GATE			IN
7			Cin  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			Cout 				74HCXX:GATE			OUT
10			S3  				74HCXX:GATE			OUT
11			B3  				74HCXX:GATE			IN
12			A3  				74HCXX:GATE			IN
13			S2  				74HCXX:GATE			OUT
14			A2  				74HCXX:GATE			IN
15			B2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC283_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S1					74HCXX:GATE			OUT
2			B1					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			S0					74HCXX:GATE			OUT
5			A0					74HCXX:GATE			IN
6			B0					74HCXX:GATE			IN
7			Cin  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			Cout 				74HCXX:GATE			OUT
10			S3  				74HCXX:GATE			OUT
11			B3  				74HCXX:GATE			IN
12			A3  				74HCXX:GATE			IN
13			S2  				74HCXX:GATE			OUT
14			A2  				74HCXX:GATE			IN
15			B2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC292_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			E 					74HCXX:GATE			IN
3			TP1  				74HCXX:GATE			OUT
4			CLK1 				74HCXX:GATE			IN
5			CLK2 				74HCXX:GATE			IN
6			TP2  				74HCXX:GATE			OUT
7			Q 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			NC					NC						NA
10			A					74HCXX:GATE			IN
11			CLR-				74HCXX:GATE			IN
12			NC  				NC						NA
13			TP3 				74HCXX:GATE			OUT
14			D					74HCXX:GATE			IN
15			C					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC292_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			E 					74HCXX:GATE			IN
3			TP1  				74HCXX:GATE			OUT
4			CLK1 				74HCXX:GATE			IN
5			CLK2 				74HCXX:GATE			IN
6			TP2  				74HCXX:GATE			OUT
7			Q 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			NC					NC						NA
10			A					74HCXX:GATE			IN
11			CLR-				74HCXX:GATE			IN
12			NC  				NC						NA
13			TP3 				74HCXX:GATE			OUT
14			D					74HCXX:GATE			IN
15			C					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC294_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			TP					74HCXX:GATE			OUT
4			CLK1 				74HCXX:GATE			IN
5			CLK2 				74HCXX:GATE			IN
6			NC					NC						NA
7			Q 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			NC					NC						NA
10			NC  				NC						NA
11			CLR-				74HCXX:GATE			IN
12			NC  				NC						NA
13			NC  				NC						NA
14			D					74HCXX:GATE			OUT
15			C					74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC294_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			TP					74HCXX:GATE			OUT
4			CLK1 				74HCXX:GATE			IN
5			CLK2 				74HCXX:GATE			IN
6			NC					NC						NA
7			Q 					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			NC					NC						NA
10			NC  				NC						NA
11			CLR-				74HCXX:GATE			IN
12			NC  				NC						NA
13			NC  				NC						NA
14			D					74HCXX:GATE			OUT
15			C					74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC298_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B2					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			GND  				GND  					NA
9			C1					74HCXX:GATE			IN
10			WORD_SEL  		74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC298_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			B2					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			GND  				GND  					NA
9			C1					74HCXX:GATE			IN
10			WORD_SEL  		74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC298_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B2					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C2					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			GND  				GND  					NA
9			C1					74HCXX:GATE			IN
10			WORD_SEL  		74HCXX:GATE			IN
11			CLK 				74HCXX:GATE			IN
12			QD  				74HCXX:GATE			OUT
13			QC  				74HCXX:GATE			OUT
14			QB  				74HCXX:GATE			OUT
15			QA  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC299_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC299_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC299_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC299_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC323_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC323_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC323_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC323_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			OE1- 				74HCXX:GATE			IN
3			OE2- 				74HCXX:GATE			IN
4			I/O_6				74HCXX:GATE			BIDIR
5			I/O_4				74HCXX:GATE			BIDIR
6			I/O_2				74HCXX:GATE			BIDIR
7			I/O_0				74HCXX:GATE			BIDIR
8			Q0					74HCXX:GATE			IN
9			MR-  				74HCXX:GATE			IN
10			GND 				GND  					NA
11			DSO 				74HCXX:GATE			IN
12			CP  				74HCXX:GATE			IN
13			I/O_1  			74HCXX:GATE			BIDIR
14			I/O_3  			74HCXX:GATE			BIDIR
15			I/O_5  			74HCXX:GATE			BIDIR
16			I/O_7  			74HCXX:GATE			BIDIR
17			Q7  				74HCXX:GATE			IN
18			DS7 				74HCXX:GATE			IN
19			S1  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC352_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC352_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC352_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B 					74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			OUT
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A					74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC353_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC353_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC353_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			B_SEL				74HCXX:GATE			IN
3			1C3  				74HCXX:GATE			IN
4			1C2  				74HCXX:GATE			IN
5			1C1  				74HCXX:GATE			IN
6			1C0  				74HCXX:GATE			IN
7			Y1					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y2					74HCXX:GATE			ENBO
10			2C0 				74HCXX:GATE			IN
11			2C1 				74HCXX:GATE			IN
12			2C2 				74HCXX:GATE			IN
13			2C3 				74HCXX:GATE			IN
14			A_SEL  			74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC354_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC354_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC354_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC354_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC356_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC356_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC356_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC356_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			D7					74HCXX:GATE			IN
2			D6					74HCXX:GATE			IN
3			D5					74HCXX:GATE			IN
4			D4					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			D2					74HCXX:GATE			IN
7			D1					74HCXX:GATE			IN
8			DO					74HCXX:GATE			IN
9			DC-/CLK 			74HCXX:GATE			IN
10			GND 				GND  					NA
11			SC- 				74HCXX:GATE			IN
12			S2  				74HCXX:GATE			IN
13			S1  				74HCXX:GATE			IN
14			S0  				74HCXX:GATE			IN
15			G1  				74HCXX:GATE			IN
16			G2  				74HCXX:GATE			IN
17			G3  				74HCXX:GATE			IN
18			W					74HCXX:GATE			ENBO
19			Y					74HCXX:GATE			ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC365_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:LINE-DRV  	ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:LINE-DRV  	ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:LINE-DRV  	ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC365_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:LINE-DRV  	ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:LINE-DRV  	ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:LINE-DRV  	ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC365_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:LINE-DRV  	ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:LINE-DRV  	ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:LINE-DRV  	ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC366_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:GATE			ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:GATE			ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:GATE			ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:GATE			ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC366_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:GATE			ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:GATE			ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:GATE			ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:GATE			ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC366_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			G1-  				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			ENBO
4			A2					74HCXX:GATE			IN
5			Y2					74HCXX:GATE			ENBO
6			A3					74HCXX:GATE			IN
7			Y3					74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			Y4					74HCXX:GATE			ENBO
10			A4  				74HCXX:GATE			IN
11			Y5  				74HCXX:GATE			ENBO
12			A5  				74HCXX:GATE			IN
13			Y6  				74HCXX:GATE			ENBO
14			A6  				74HCXX:GATE			IN
15			G2- 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC367_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:LINE-DRV  	ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:LINE-DRV  	ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:LINE-DRV  	ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC367_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:LINE-DRV  	ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:LINE-DRV  	ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:LINE-DRV  	ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC367_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:LINE-DRV  	ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:LINE-DRV  	ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:LINE-DRV  	ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:LINE-DRV  	ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:LINE-DRV  	ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC368_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:GATE			ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:GATE			ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:GATE			ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:GATE			ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:GATE			ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC368_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:GATE			ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:GATE			ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:GATE			ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:GATE			ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:GATE			ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC368_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			1A1  				74HCXX:GATE			IN
3			1Y1  				74HCXX:GATE			ENBO
4			1A2  				74HCXX:GATE			IN
5			1Y2  				74HCXX:GATE			ENBO
6			1A3  				74HCXX:GATE			IN
7			1Y3  				74HCXX:GATE			ENBO
8			GND  				GND  					NA
9			1Y4  				74HCXX:GATE			ENBO
10			1A4 				74HCXX:GATE			IN
11			2Y1 				74HCXX:GATE			ENBO
12			2A1 				74HCXX:GATE			IN
13			2Y2 				74HCXX:GATE			ENBO
14			2A2 				74HCXX:GATE			IN
15			OE2-				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC373_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1					74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:LINE-DRV  	ENBO
6			Q3					74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LE- 				74HCXX:GATE			IN
12			Q5  				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:LINE-DRV  	ENBO
16			Q7  				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC373_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1					74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:LINE-DRV  	ENBO
6			Q3					74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LE- 				74HCXX:GATE			IN
12			Q5  				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:LINE-DRV  	ENBO
16			Q7  				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC373_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1					74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:LINE-DRV  	ENBO
6			Q3					74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LE- 				74HCXX:GATE			IN
12			Q5  				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:LINE-DRV  	ENBO
16			Q7  				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC373_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1					74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:LINE-DRV  	ENBO
6			Q3					74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LE- 				74HCXX:GATE			IN
12			Q5  				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:LINE-DRV  	ENBO
16			Q7  				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC374_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q0					74HCXX:LINE-DRV  	ENBO
3			D0					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			Q1					74HCXX:LINE-DRV  	ENBO
6			Q2					74HCXX:LINE-DRV  	ENBO
7			D2					74HCXX:GATE			IN
8			D3					74HCXX:GATE			IN
9			Q3					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CP  				74HCXX:GATE			IN
12			Q4  				74HCXX:LINE-DRV  	ENBO
13			D4  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q6  				74HCXX:LINE-DRV  	ENBO
17			D6  				74HCXX:GATE			IN
18			D7  				74HCXX:GATE			IN
19			Q7  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC374_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q0					74HCXX:LINE-DRV  	ENBO
3			D0					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			Q1					74HCXX:LINE-DRV  	ENBO
6			Q2					74HCXX:LINE-DRV  	ENBO
7			D2					74HCXX:GATE			IN
8			D3					74HCXX:GATE			IN
9			Q3					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CP  				74HCXX:GATE			IN
12			Q4  				74HCXX:LINE-DRV  	ENBO
13			D4  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q6  				74HCXX:LINE-DRV  	ENBO
17			D6  				74HCXX:GATE			IN
18			D7  				74HCXX:GATE			IN
19			Q7  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC374_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q0					74HCXX:LINE-DRV  	ENBO
3			D0					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			Q1					74HCXX:LINE-DRV  	ENBO
6			Q2					74HCXX:LINE-DRV  	ENBO
7			D2					74HCXX:GATE			IN
8			D3					74HCXX:GATE			IN
9			Q3					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CP  				74HCXX:GATE			IN
12			Q4  				74HCXX:LINE-DRV  	ENBO
13			D4  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q6  				74HCXX:LINE-DRV  	ENBO
17			D6  				74HCXX:GATE			IN
18			D7  				74HCXX:GATE			IN
19			Q7  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC374_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q0					74HCXX:LINE-DRV  	ENBO
3			D0					74HCXX:GATE			IN
4			D1					74HCXX:GATE			IN
5			Q1					74HCXX:LINE-DRV  	ENBO
6			Q2					74HCXX:LINE-DRV  	ENBO
7			D2					74HCXX:GATE			IN
8			D3					74HCXX:GATE			IN
9			Q3					74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CP  				74HCXX:GATE			IN
12			Q4  				74HCXX:LINE-DRV  	ENBO
13			D4  				74HCXX:GATE			IN
14			D5  				74HCXX:GATE			IN
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q6  				74HCXX:LINE-DRV  	ENBO
17			D6  				74HCXX:GATE			IN
18			D7  				74HCXX:GATE			IN
19			Q7  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC375_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			ENABLE_1->2		74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			D2					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D3					74HCXX:GATE			IN
10			Q3- 				74HCXX:GATE			OUT
11			Q3  				74HCXX:GATE			OUT
12			ENABLE_3->4  	74HCXX:GATE			IN
13			Q4  				74HCXX:GATE			OUT
14			Q4- 				74HCXX:GATE			OUT
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC375_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			D1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			ENABLE_1->2		74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			D2					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D3					74HCXX:GATE			IN
10			Q3- 				74HCXX:GATE			OUT
11			Q3  				74HCXX:GATE			OUT
12			ENABLE_3->4  	74HCXX:GATE			IN
13			Q4  				74HCXX:GATE			OUT
14			Q4- 				74HCXX:GATE			OUT
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC375_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			D1					74HCXX:GATE			IN
2			Q1-  				74HCXX:GATE			OUT
3			Q1					74HCXX:GATE			OUT
4			ENABLE_1->2		74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q2-  				74HCXX:GATE			OUT
7			D2					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D3					74HCXX:GATE			IN
10			Q3- 				74HCXX:GATE			OUT
11			Q3  				74HCXX:GATE			OUT
12			ENABLE_3->4  	74HCXX:GATE			IN
13			Q4  				74HCXX:GATE			OUT
14			Q4- 				74HCXX:GATE			OUT
15			D4  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC377_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CE-  				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC377_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			CE-  				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC377_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CE-  				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC377_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			CE-  				74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			Q3					74HCXX:GATE			OUT
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4					74HCXX:GATE			OUT
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			Q7  				74HCXX:GATE			OUT
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8  				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC378_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC378_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC378_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2					74HCXX:GATE			OUT
6			D3					74HCXX:GATE			IN
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q4  				74HCXX:GATE			OUT
11			D4  				74HCXX:GATE			IN
12			Q5  				74HCXX:GATE			OUT
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC379_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC379_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC379_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			ENABLE_G-  		74HCXX:GATE			IN
2			Q1					74HCXX:GATE			OUT
3			Q1-  				74HCXX:GATE			OUT
4			D1					74HCXX:GATE			IN
5			D2					74HCXX:GATE			IN
6			Q2-  				74HCXX:GATE			OUT
7			Q2					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLK  				74HCXX:GATE			IN
10			Q3  				74HCXX:GATE			OUT
11			Q3- 				74HCXX:GATE			OUT
12			D3  				74HCXX:GATE			IN
13			D4  				74HCXX:GATE			IN
14			Q4- 				74HCXX:GATE			OUT
15			Q4  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC386_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC386_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC386_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC386_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC390_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			B1					74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			B2  				74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			A2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC390_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			B1					74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			B2  				74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			A2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC390_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			B1					74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			B2  				74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			A2  				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC393_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			Q1_B 				74HCXX:GATE			OUT
5			Q1_C 				74HCXX:GATE			OUT
6			Q1_D 				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2_D 				74HCXX:GATE			OUT
9			Q2_C 				74HCXX:GATE			OUT
10			Q2_B				74HCXX:GATE			OUT
11			Q2_A				74HCXX:GATE			OUT
12			CLR_2  			74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC393_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			Q1_B 				74HCXX:GATE			OUT
5			Q1_C 				74HCXX:GATE			OUT
6			Q1_D 				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2_D 				74HCXX:GATE			OUT
9			Q2_C 				74HCXX:GATE			OUT
10			Q2_B				74HCXX:GATE			OUT
11			Q2_A				74HCXX:GATE			OUT
12			CLR_2  			74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC393_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			Q1_B 				74HCXX:GATE			OUT
5			Q1_C 				74HCXX:GATE			OUT
6			Q1_D 				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2_D 				74HCXX:GATE			OUT
9			Q2_C 				74HCXX:GATE			OUT
10			Q2_B				74HCXX:GATE			OUT
11			Q2_A				74HCXX:GATE			OUT
12			CLR_2  			74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC393_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			Q1_B 				74HCXX:GATE			OUT
5			Q1_C 				74HCXX:GATE			OUT
6			Q1_D 				74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Q2_D 				74HCXX:GATE			OUT
9			Q2_C 				74HCXX:GATE			OUT
10			Q2_B				74HCXX:GATE			OUT
11			Q2_A				74HCXX:GATE			OUT
12			CLR_2  			74HCXX:GATE			IN
13			A2  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC423_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC423_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			CLR_1				74HCXX:GATE			IN
4			Q1-  				74HCXX:GATE			OUT
5			Q2					74HCXX:GATE			OUT
6			C2(ext) 			ANALOG  				NA
7			2R(ext)/C(ext)	ANALOG  				NA
8			GND  				GND  					NA
9			A2					74HCXX:GATE			IN
10			B2  				74HCXX:GATE			IN
11			CLR_2  			74HCXX:GATE			IN
12			Q2- 				74HCXX:GATE			OUT
13			Q1  				74HCXX:GATE			OUT
14			C1(ext)			ANALOG  				NA
15			1R(ext)/C(ext)  ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC490_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			1_SET_TO_9 		74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			2_SET_TO_9		74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			CLK_2  			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC490_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			1_SET_TO_9 		74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			2_SET_TO_9		74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			CLK_2  			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC490_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK_1				74HCXX:GATE			IN
2			CLR_1				74HCXX:GATE			IN
3			Q1_A 				74HCXX:GATE			OUT
4			1_SET_TO_9 		74HCXX:GATE			IN
5			Q1_B 				74HCXX:GATE			OUT
6			Q1_C 				74HCXX:GATE			OUT
7			Q1_D 				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q2_D 				74HCXX:GATE			OUT
10			Q2_C				74HCXX:GATE			OUT
11			Q2_B				74HCXX:GATE			OUT
12			2_SET_TO_9		74HCXX:GATE			IN
13			Q2_A				74HCXX:GATE			OUT
14			CLR_2  			74HCXX:GATE			IN
15			CLK_2  			74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC521_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			(P=Q)- 			74HCXX:GATE			IN
19			CLK_B  			74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC521_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			(P=Q)- 			74HCXX:GATE			IN
19			CLK_B  			74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC521_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			(P=Q)- 			74HCXX:GATE			IN
19			CLK_B  			74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC521_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			(P=Q)- 			74HCXX:GATE			IN
19			CLK_B  			74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC533_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LATCH_ENB 		74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC533_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LATCH_ENB 		74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC533_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LATCH_ENB 		74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC533_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			LATCH_ENB 		74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC534_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC534_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC534_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC534_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			Q1-  				74HCXX:LINE-DRV  	ENBO
3			D1					74HCXX:GATE			IN
4			D2					74HCXX:GATE			IN
5			Q2-  				74HCXX:LINE-DRV  	ENBO
6			Q3-  				74HCXX:LINE-DRV  	ENBO
7			D3					74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:LINE-DRV  	ENBO
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q5- 				74HCXX:LINE-DRV  	ENBO
13			D5  				74HCXX:GATE			IN
14			D6  				74HCXX:GATE			IN
15			Q6- 				74HCXX:LINE-DRV  	ENBO
16			Q7- 				74HCXX:LINE-DRV  	ENBO
17			D7  				74HCXX:GATE			IN
18			D8  				74HCXX:GATE			IN
19			Q8- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC540_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC540_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC540_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC540_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC541_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC541_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC541_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC541_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE1- 				74HCXX:GATE			IN
2			A1					74HCXX:GATE			IN
3			A2					74HCXX:GATE			IN
4			A3					74HCXX:GATE			IN
5			A4					74HCXX:GATE			IN
6			A5					74HCXX:GATE			IN
7			A6					74HCXX:GATE			IN
8			A7					74HCXX:GATE			IN
9			A8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			Y8  				74HCXX:LINE-DRV  	ENBO
12			Y7  				74HCXX:LINE-DRV  	ENBO
13			Y6  				74HCXX:LINE-DRV  	ENBO
14			Y5  				74HCXX:LINE-DRV  	ENBO
15			Y4  				74HCXX:LINE-DRV  	ENBO
16			Y3  				74HCXX:LINE-DRV  	ENBO
17			Y2  				74HCXX:LINE-DRV  	ENBO
18			Y1  				74HCXX:LINE-DRV  	ENBO
19			OE2-				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC543_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC543_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC543_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC543_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC544_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC544_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC544_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC544_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:GATE			BIDIR
2			A4					74HCXX:GATE			BIDIR
3			A5					74HCXX:GATE			BIDIR
4			A6					74HCXX:GATE			BIDIR
5			A7					74HCXX:GATE			BIDIR
6			VCC  				POWER					NA
7			B7					74HCXX:GATE			BIDIR
8			B6					74HCXX:GATE			BIDIR
9			B5					74HCXX:GATE			BIDIR
10			B4  				74HCXX:GATE			BIDIR
11			B3  				74HCXX:GATE			BIDIR
12			B2  				74HCXX:GATE			BIDIR
13			B1  				74HCXX:GATE			BIDIR
14			B0  				74HCXX:GATE			BIDIR
15			OEBA-  			74HCXX:GATE			IN
16			LEAB-  			74HCXX:GATE			IN
17			EAB-				74HCXX:GATE			IN
18			GND 				GND  					NA
19			EBA-				74HCXX:GATE			IN
20			LEBA-  			74HCXX:GATE			IN
21			OEAB-  			74HCXX:GATE			IN
22			A0  				74HCXX:GATE			BIDIR
23			A1  				74HCXX:GATE			BIDIR
24			A2  				74HCXX:GATE			BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC550_DIP
[Model File]		PML.MOD
[Package Model]    DIP28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:LINE-DRV  	BIDIR
2			A4					74HCXX:LINE-DRV  	BIDIR
3			A5					74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6					74HCXX:LINE-DRV  	BIDIR
7			A7					74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7					74HCXX:LINE-DRV  	BIDIR
10			B6  				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5  				74HCXX:LINE-DRV  	BIDIR
14			B4  				74HCXX:LINE-DRV  	BIDIR
15			B3  				74HCXX:LINE-DRV  	BIDIR
16			B2  				74HCXX:LINE-DRV  	BIDIR
17			B1  				74HCXX:LINE-DRV  	BIDIR
18			B0  				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0  				74HCXX:LINE-DRV  	BIDIR
27			A1  				74HCXX:LINE-DRV  	BIDIR
28			A2  				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC550_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:LINE-DRV  	BIDIR
2			A4					74HCXX:LINE-DRV  	BIDIR
3			A5					74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6					74HCXX:LINE-DRV  	BIDIR
7			A7					74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7					74HCXX:LINE-DRV  	BIDIR
10			B6  				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5  				74HCXX:LINE-DRV  	BIDIR
14			B4  				74HCXX:LINE-DRV  	BIDIR
15			B3  				74HCXX:LINE-DRV  	BIDIR
16			B2  				74HCXX:LINE-DRV  	BIDIR
17			B1  				74HCXX:LINE-DRV  	BIDIR
18			B0  				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0  				74HCXX:LINE-DRV  	BIDIR
27			A1  				74HCXX:LINE-DRV  	BIDIR
28			A2  				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC550_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3					74HCXX:LINE-DRV  	BIDIR
2			A4					74HCXX:LINE-DRV  	BIDIR
3			A5					74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6					74HCXX:LINE-DRV  	BIDIR
7			A7					74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7					74HCXX:LINE-DRV  	BIDIR
10			B6  				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5  				74HCXX:LINE-DRV  	BIDIR
14			B4  				74HCXX:LINE-DRV  	BIDIR
15			B3  				74HCXX:LINE-DRV  	BIDIR
16			B2  				74HCXX:LINE-DRV  	BIDIR
17			B1  				74HCXX:LINE-DRV  	BIDIR
18			B0  				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0  				74HCXX:LINE-DRV  	BIDIR
27			A1  				74HCXX:LINE-DRV  	BIDIR
28			A2  				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC551_DIP
[Model File]		PML.MOD
[Package Model]    DIP28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3-  				74HCXX:LINE-DRV  	BIDIR
2			A4-  				74HCXX:LINE-DRV  	BIDIR
3			A5-  				74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6-  				74HCXX:LINE-DRV  	BIDIR
7			A7-  				74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7-  				74HCXX:LINE-DRV  	BIDIR
10			B6- 				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5- 				74HCXX:LINE-DRV  	BIDIR
14			B4- 				74HCXX:LINE-DRV  	BIDIR
15			B3- 				74HCXX:LINE-DRV  	BIDIR
16			B2- 				74HCXX:LINE-DRV  	BIDIR
17			B1- 				74HCXX:LINE-DRV  	BIDIR
18			B0- 				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0- 				74HCXX:LINE-DRV  	BIDIR
27			A1- 				74HCXX:LINE-DRV  	BIDIR
28			A2- 				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC551_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3-  				74HCXX:LINE-DRV  	BIDIR
2			A4-  				74HCXX:LINE-DRV  	BIDIR
3			A5-  				74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6-  				74HCXX:LINE-DRV  	BIDIR
7			A7-  				74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7-  				74HCXX:LINE-DRV  	BIDIR
10			B6- 				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5- 				74HCXX:LINE-DRV  	BIDIR
14			B4- 				74HCXX:LINE-DRV  	BIDIR
15			B3- 				74HCXX:LINE-DRV  	BIDIR
16			B2- 				74HCXX:LINE-DRV  	BIDIR
17			B1- 				74HCXX:LINE-DRV  	BIDIR
18			B0- 				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0- 				74HCXX:LINE-DRV  	BIDIR
27			A1- 				74HCXX:LINE-DRV  	BIDIR
28			A2- 				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC551_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP28
|
[Pin]		signal_name 	model_name  		direction
|
1			A3-  				74HCXX:LINE-DRV  	BIDIR
2			A4-  				74HCXX:LINE-DRV  	BIDIR
3			A5-  				74HCXX:LINE-DRV  	BIDIR
4			CFBA 				74HCXX:GATE			IN
5			FBA  				74HCXX:GATE			IN
6			A6-  				74HCXX:LINE-DRV  	BIDIR
7			A7-  				74HCXX:LINE-DRV  	BIDIR
8			VCC  				POWER					NA
9			B7-  				74HCXX:LINE-DRV  	BIDIR
10			B6- 				74HCXX:LINE-DRV  	BIDIR
11			FAB 				74HCXX:GATE			IN
12			CFAB				74HCXX:GATE			IN
13			B5- 				74HCXX:LINE-DRV  	BIDIR
14			B4- 				74HCXX:LINE-DRV  	BIDIR
15			B3- 				74HCXX:LINE-DRV  	BIDIR
16			B2- 				74HCXX:LINE-DRV  	BIDIR
17			B1- 				74HCXX:LINE-DRV  	BIDIR
18			B0- 				74HCXX:LINE-DRV  	BIDIR
19			OEB-				74HCXX:GATE			IN
20			CPA 				74HCXX:GATE			IN
21			CEA-				74HCXX:GATE			IN
22			GND 				GND  					NA
23			CEB-				74HCXX:GATE			IN
24			CPB 				74HCXX:GATE			IN
25			OEA-				74HCXX:GATE			IN
26			A0- 				74HCXX:LINE-DRV  	BIDIR
27			A1- 				74HCXX:LINE-DRV  	BIDIR
28			A2- 				74HCXX:LINE-DRV  	BIDIR
|
|==============================================================================
|==============================================================================
[Component]			74HC563_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC563_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC563_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC563_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC564_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC564_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC564_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC564_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OUT_CTRL			74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LATCH_ENBL		74HCXX:GATE			IN
12			Q8- 				74HCXX:LINE-DRV  	ENBO
13			Q7- 				74HCXX:LINE-DRV  	ENBO
14			Q6- 				74HCXX:LINE-DRV  	ENBO
15			Q5- 				74HCXX:LINE-DRV  	ENBO
16			Q4- 				74HCXX:LINE-DRV  	ENBO
17			Q3- 				74HCXX:LINE-DRV  	ENBO
18			Q2- 				74HCXX:LINE-DRV  	ENBO
19			Q1- 				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC573_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LE  				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC573_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LE  				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC573_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LE  				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC573_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			LE  				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC574_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC574_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC574_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC574_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			OE-  				74HCXX:GATE			IN
2			D1					74HCXX:GATE			IN
3			D2					74HCXX:GATE			IN
4			D3					74HCXX:GATE			IN
5			D4					74HCXX:GATE			IN
6			D5					74HCXX:GATE			IN
7			D6					74HCXX:GATE			IN
8			D7					74HCXX:GATE			IN
9			D8					74HCXX:GATE			IN
10			GND 				GND  					NA
11			CLK 				74HCXX:GATE			IN
12			Q8  				74HCXX:LINE-DRV  	ENBO
13			Q7  				74HCXX:LINE-DRV  	ENBO
14			Q6  				74HCXX:LINE-DRV  	ENBO
15			Q5  				74HCXX:LINE-DRV  	ENBO
16			Q4  				74HCXX:LINE-DRV  	ENBO
17			Q3  				74HCXX:LINE-DRV  	ENBO
18			Q2  				74HCXX:LINE-DRV  	ENBO
19			Q1  				74HCXX:LINE-DRV  	ENBO
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC589_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			QH'  				74HCXX:OPEN-COL  	OUT
10			OE- 				74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			SLOAD- 			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC589_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			QH'  				74HCXX:OPEN-COL  	OUT
10			OE- 				74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			SLOAD- 			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC590_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			RCO- 				74HCXX:GATE			OUT
10			CCLR-  			74HCXX:GATE			IN
11			CCK 				74HCXX:GATE			IN
12			CCKEN- 			74HCXX:GATE			IN
13			RCK 				74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC590_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			RCO- 				74HCXX:GATE			OUT
10			CCLR-  			74HCXX:GATE			IN
11			CCK 				74HCXX:GATE			IN
12			CCKEN- 			74HCXX:GATE			IN
13			RCK 				74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC590_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			RCO- 				74HCXX:GATE			OUT
10			CCLR-  			74HCXX:GATE			IN
11			CCK 				74HCXX:GATE			IN
12			CCKEN- 			74HCXX:GATE			IN
13			RCK 				74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC592_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			RCO- 				74HCXX:GATE			OUT
10			CCLR-  			74HCXX:GATE			IN
11			CCK 				74HCXX:GATE			IN
12			CCKEN- 			74HCXX:GATE			IN
13			RCK 				74HCXX:GATE			IN
14			CLOAD- 			74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC592_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			RCO- 				74HCXX:GATE			OUT
10			CCLR-  			74HCXX:GATE			IN
11			CCK 				74HCXX:GATE			IN
12			CCKEN- 			74HCXX:GATE			IN
13			RCK 				74HCXX:GATE			IN
14			CLOAD- 			74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC593_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A/QA 				74HCXX:GATE			IN
2			B/QB 				74HCXX:LINE-DRV  	BIDIR
3			C/QC 				74HCXX:LINE-DRV  	BIDIR
4			D/QD 				74HCXX:LINE-DRV  	BIDIR
5			E/QE 				74HCXX:LINE-DRV  	BIDIR
6			F/QF 				74HCXX:LINE-DRV  	BIDIR
7			G/QG 				74HCXX:LINE-DRV  	BIDIR
8			H/QH 				74HCXX:LINE-DRV  	BIDIR
9			CLOAD-  			74HCXX:GATE			IN
10			GND 				GND  					NA
11			RCO-				74HCXX:GATE			OUT
12			CCLR-  			74HCXX:GATE			IN
13			CCK 				74HCXX:GATE			IN
14			CCKEN- 			74HCXX:GATE			IN
15			CCKEN  			74HCXX:GATE			IN
16			RCK 				74HCXX:GATE			IN
17			RCKEN- 			74HCXX:GATE			IN
18			G-  				74HCXX:GATE			IN
19			G					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC593_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A/QA 				74HCXX:GATE			IN
2			B/QB 				74HCXX:LINE-DRV  	BIDIR
3			C/QC 				74HCXX:LINE-DRV  	BIDIR
4			D/QD 				74HCXX:LINE-DRV  	BIDIR
5			E/QE 				74HCXX:LINE-DRV  	BIDIR
6			F/QF 				74HCXX:LINE-DRV  	BIDIR
7			G/QG 				74HCXX:LINE-DRV  	BIDIR
8			H/QH 				74HCXX:LINE-DRV  	BIDIR
9			CLOAD-  			74HCXX:GATE			IN
10			GND 				GND  					NA
11			RCO-				74HCXX:GATE			OUT
12			CCLR-  			74HCXX:GATE			IN
13			CCK 				74HCXX:GATE			IN
14			CCKEN- 			74HCXX:GATE			IN
15			CCKEN  			74HCXX:GATE			IN
16			RCK 				74HCXX:GATE			IN
17			RCKEN- 			74HCXX:GATE			IN
18			G-  				74HCXX:GATE			IN
19			G					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC593_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A/QA 				74HCXX:GATE			IN
2			B/QB 				74HCXX:LINE-DRV  	BIDIR
3			C/QC 				74HCXX:LINE-DRV  	BIDIR
4			D/QD 				74HCXX:LINE-DRV  	BIDIR
5			E/QE 				74HCXX:LINE-DRV  	BIDIR
6			F/QF 				74HCXX:LINE-DRV  	BIDIR
7			G/QG 				74HCXX:LINE-DRV  	BIDIR
8			H/QH 				74HCXX:LINE-DRV  	BIDIR
9			CLOAD-  			74HCXX:GATE			IN
10			GND 				GND  					NA
11			RCO-				74HCXX:GATE			OUT
12			CCLR-  			74HCXX:GATE			IN
13			CCK 				74HCXX:GATE			IN
14			CCKEN- 			74HCXX:GATE			IN
15			CCKEN  			74HCXX:GATE			IN
16			RCK 				74HCXX:GATE			IN
17			RCKEN- 			74HCXX:GATE			IN
18			G-  				74HCXX:GATE			IN
19			G					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC593_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A/QA 				74HCXX:GATE			IN
2			B/QB 				74HCXX:LINE-DRV  	BIDIR
3			C/QC 				74HCXX:LINE-DRV  	BIDIR
4			D/QD 				74HCXX:LINE-DRV  	BIDIR
5			E/QE 				74HCXX:LINE-DRV  	BIDIR
6			F/QF 				74HCXX:LINE-DRV  	BIDIR
7			G/QG 				74HCXX:LINE-DRV  	BIDIR
8			H/QH 				74HCXX:LINE-DRV  	BIDIR
9			CLOAD-  			74HCXX:GATE			IN
10			GND 				GND  					NA
11			RCO-				74HCXX:GATE			OUT
12			CCLR-  			74HCXX:GATE			IN
13			CCK 				74HCXX:GATE			IN
14			CCKEN- 			74HCXX:GATE			IN
15			CCKEN  			74HCXX:GATE			IN
16			RCK 				74HCXX:GATE			IN
17			RCKEN- 			74HCXX:GATE			IN
18			G-  				74HCXX:GATE			IN
19			G					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC594_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	OUT
2			QC					74HCXX:LINE-DRV  	OUT
3			QD					74HCXX:LINE-DRV  	OUT
4			QE					74HCXX:LINE-DRV  	OUT
5			QF					74HCXX:LINE-DRV  	OUT
6			QG					74HCXX:LINE-DRV  	OUT
7			QH					74HCXX:LINE-DRV  	OUT
8			GND  				GND  					NA
9			QH'  				74HCXX:LINE-DRV  	OUT
10			SRCLR- 			74HCXX:GATE			IN
11			SRCK				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			RCLR-  			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC594_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	OUT
2			QC					74HCXX:LINE-DRV  	OUT
3			QD					74HCXX:LINE-DRV  	OUT
4			QE					74HCXX:LINE-DRV  	OUT
5			QF					74HCXX:LINE-DRV  	OUT
6			QG					74HCXX:LINE-DRV  	OUT
7			QH					74HCXX:LINE-DRV  	OUT
8			GND  				GND  					NA
9			QH'  				74HCXX:LINE-DRV  	OUT
10			SRCLR- 			74HCXX:GATE			IN
11			SRCK				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			RCLR-  			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC594_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	OUT
2			QC					74HCXX:LINE-DRV  	OUT
3			QD					74HCXX:LINE-DRV  	OUT
4			QE					74HCXX:LINE-DRV  	OUT
5			QF					74HCXX:LINE-DRV  	OUT
6			QG					74HCXX:LINE-DRV  	OUT
7			QH					74HCXX:LINE-DRV  	OUT
8			GND  				GND  					NA
9			QH'  				74HCXX:LINE-DRV  	OUT
10			SRCLR- 			74HCXX:GATE			IN
11			SRCK				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			RCLR-  			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC595_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			QH'  				74HCXX:GATE			OUT
10			SCLR-  			74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			G-  				74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC595_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			QH'  				74HCXX:GATE			OUT
10			SCLR-  			74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			G-  				74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC595_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QB					74HCXX:LINE-DRV  	ENBO
2			QC					74HCXX:LINE-DRV  	ENBO
3			QD					74HCXX:LINE-DRV  	ENBO
4			QE					74HCXX:LINE-DRV  	ENBO
5			QF					74HCXX:LINE-DRV  	ENBO
6			QG					74HCXX:LINE-DRV  	ENBO
7			QH					74HCXX:LINE-DRV  	ENBO
8			GND  				GND  					NA
9			QH'  				74HCXX:GATE			OUT
10			SCLR-  			74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			G-  				74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			QA  				74HCXX:LINE-DRV  	ENBO
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC597_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			QH'  				74HCXX:LINE-DRV  	OUT
10			SCLR-  			74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			SLOAD- 			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC597_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			B 					74HCXX:GATE			IN
2			C 					74HCXX:GATE			IN
3			D 					74HCXX:GATE			IN
4			E 					74HCXX:GATE			IN
5			F 					74HCXX:GATE			IN
6			G 					74HCXX:GATE			IN
7			H 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			QH'  				74HCXX:LINE-DRV  	OUT
10			SCLR-  			74HCXX:GATE			IN
11			SCK 				74HCXX:GATE			IN
12			RCK 				74HCXX:GATE			IN
13			SLOAD- 			74HCXX:GATE			IN
14			SER 				74HCXX:GATE			IN
15			A					74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC604_DIP
[Model File]		PML.MOD
[Package Model]    DIP28
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			SEL_A/B-			74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			A4					74HCXX:GATE			IN
10			B4  				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	OUT
12			Y3  				74HCXX:LINE-DRV  	OUT
13			Y2  				74HCXX:LINE-DRV  	OUT
14			GND 				GND  					NA
15			Y1  				74HCXX:LINE-DRV  	OUT
16			Y5  				74HCXX:LINE-DRV  	OUT
17			Y6  				74HCXX:LINE-DRV  	OUT
18			Y7  				74HCXX:LINE-DRV  	OUT
19			Y8  				74HCXX:LINE-DRV  	OUT
20			B8  				74HCXX:GATE			IN
21			A8  				74HCXX:GATE			IN
22			B7  				74HCXX:GATE			IN
23			A7  				74HCXX:GATE			IN
24			B6  				74HCXX:GATE			IN
25			A6  				74HCXX:GATE			IN
26			B5  				74HCXX:GATE			IN
27			A5  				74HCXX:GATE			IN
28			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC604_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC28
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			SEL_A/B-			74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			A4					74HCXX:GATE			IN
10			B4  				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	OUT
12			Y3  				74HCXX:LINE-DRV  	OUT
13			Y2  				74HCXX:LINE-DRV  	OUT
14			GND 				GND  					NA
15			Y1  				74HCXX:LINE-DRV  	OUT
16			Y5  				74HCXX:LINE-DRV  	OUT
17			Y6  				74HCXX:LINE-DRV  	OUT
18			Y7  				74HCXX:LINE-DRV  	OUT
19			Y8  				74HCXX:LINE-DRV  	OUT
20			B8  				74HCXX:GATE			IN
21			A8  				74HCXX:GATE			IN
22			B7  				74HCXX:GATE			IN
23			A7  				74HCXX:GATE			IN
24			B6  				74HCXX:GATE			IN
25			A6  				74HCXX:GATE			IN
26			B5  				74HCXX:GATE			IN
27			A5  				74HCXX:GATE			IN
28			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC604_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP28
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK  				74HCXX:GATE			IN
2			SEL_A/B-			74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			A4					74HCXX:GATE			IN
10			B4  				74HCXX:GATE			IN
11			Y4  				74HCXX:LINE-DRV  	OUT
12			Y3  				74HCXX:LINE-DRV  	OUT
13			Y2  				74HCXX:LINE-DRV  	OUT
14			GND 				GND  					NA
15			Y1  				74HCXX:LINE-DRV  	OUT
16			Y5  				74HCXX:LINE-DRV  	OUT
17			Y6  				74HCXX:LINE-DRV  	OUT
18			Y7  				74HCXX:LINE-DRV  	OUT
19			Y8  				74HCXX:LINE-DRV  	OUT
20			B8  				74HCXX:GATE			IN
21			A8  				74HCXX:GATE			IN
22			B7  				74HCXX:GATE			IN
23			A7  				74HCXX:GATE			IN
24			B6  				74HCXX:GATE			IN
25			A6  				74HCXX:GATE			IN
26			B5  				74HCXX:GATE			IN
27			A5  				74HCXX:GATE			IN
28			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC620_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			(G-)BA 			74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC620_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			(G-)BA 			74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC620_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			(G-)BA 			74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC620_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			(G-)BA 			74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC623_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			GBA-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC623_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			GBA-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC623_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			GBA-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC623_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			GBA-				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC640_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC640_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC640_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC640_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC643_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC643_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC643_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC643_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC645_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC645_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC645_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC645_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			GND 				GND  					NA
11			B8  				74HCXX:LINE-DRV  	BIDIR
12			B7  				74HCXX:LINE-DRV  	BIDIR
13			B6  				74HCXX:LINE-DRV  	BIDIR
14			B5  				74HCXX:LINE-DRV  	BIDIR
15			B4  				74HCXX:LINE-DRV  	BIDIR
16			B3  				74HCXX:LINE-DRV  	BIDIR
17			B2  				74HCXX:LINE-DRV  	BIDIR
18			B1  				74HCXX:LINE-DRV  	BIDIR
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC646_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			G-  				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC646_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			G-  				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC646_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			G-  				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC646_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			G-  				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC648_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CLOCK_AB			74HCXX:GATE			IN
2			SELECT_AB  		74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			ENB(G-)RA 		74HCXX:GATE			IN
22			SELECT_BA 		74HCXX:GATE			IN
23			CLOCK_BA  		74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC648_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			CLOCK_AB			74HCXX:GATE			IN
2			SELECT_AB  		74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			ENB(G-)RA 		74HCXX:GATE			IN
22			SELECT_BA 		74HCXX:GATE			IN
23			CLOCK_BA  		74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC648_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CLOCK_AB			74HCXX:GATE			IN
2			SELECT_AB  		74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			ENB(G-)RA 		74HCXX:GATE			IN
22			SELECT_BA 		74HCXX:GATE			IN
23			CLOCK_BA  		74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC648_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CLOCK_AB			74HCXX:GATE			IN
2			SELECT_AB  		74HCXX:GATE			IN
3			DIR  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			ENB(G-)RA 		74HCXX:GATE			IN
22			SELECT_BA 		74HCXX:GATE			IN
23			CLOCK_BA  		74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC651_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC651_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC651_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC651_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CAB  				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			GAB  				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			(G-)BA 			74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CBA 				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CPAB 				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			OEAB 				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			OEBA				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CPBA				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			CPAB 				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			OEAB 				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			OEBA				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CPBA				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CPAB 				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			OEAB 				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			OEBA				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CPBA				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC652_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			CPAB 				74HCXX:GATE			IN
2			SAB  				74HCXX:GATE			IN
3			OEAB 				74HCXX:GATE			IN
4			A1					74HCXX:LINE-DRV  	BIDIR
5			A2					74HCXX:LINE-DRV  	BIDIR
6			A3					74HCXX:LINE-DRV  	BIDIR
7			A4					74HCXX:LINE-DRV  	BIDIR
8			A5					74HCXX:LINE-DRV  	BIDIR
9			A6					74HCXX:LINE-DRV  	BIDIR
10			A7  				74HCXX:LINE-DRV  	BIDIR
11			A8  				74HCXX:LINE-DRV  	BIDIR
12			GND 				GND  					NA
13			B8  				74HCXX:LINE-DRV  	BIDIR
14			B7  				74HCXX:LINE-DRV  	BIDIR
15			B6  				74HCXX:LINE-DRV  	BIDIR
16			B5  				74HCXX:LINE-DRV  	BIDIR
17			B4  				74HCXX:LINE-DRV  	BIDIR
18			B3  				74HCXX:LINE-DRV  	BIDIR
19			B2  				74HCXX:LINE-DRV  	BIDIR
20			B1  				74HCXX:LINE-DRV  	BIDIR
21			OEBA				74HCXX:GATE			IN
22			SBA 				74HCXX:GATE			IN
23			CPBA				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC658_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC658_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC658_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC658_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC659_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC659_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC659_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC659_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			GAB  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			GBA-				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC664_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC664_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC664_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC664_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC665_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC665_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC665_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC665_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			DIR  				74HCXX:GATE			IN
2			A1					74HCXX:LINE-DRV  	BIDIR
3			A2					74HCXX:LINE-DRV  	BIDIR
4			A3					74HCXX:LINE-DRV  	BIDIR
5			A4					74HCXX:LINE-DRV  	BIDIR
6			A5					74HCXX:LINE-DRV  	BIDIR
7			A6					74HCXX:LINE-DRV  	BIDIR
8			A7					74HCXX:LINE-DRV  	BIDIR
9			A8					74HCXX:LINE-DRV  	BIDIR
10			BPI 				74HCXX:GATE			IN
11			BPO 				74HCXX:LINE-DRV  	OUT
12			GND 				GND  					NA
13			APO 				74HCXX:LINE-DRV  	OUT
14			API 				74HCXX:GATE			IN
15			B8  				74HCXX:LINE-DRV  	BIDIR
16			B7  				74HCXX:LINE-DRV  	BIDIR
17			B6  				74HCXX:LINE-DRV  	BIDIR
18			B5  				74HCXX:LINE-DRV  	BIDIR
19			B4  				74HCXX:LINE-DRV  	BIDIR
20			B3  				74HCXX:LINE-DRV  	BIDIR
21			B2  				74HCXX:LINE-DRV  	BIDIR
22			B1  				74HCXX:LINE-DRV  	BIDIR
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC677_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			C-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC677_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			C-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC677_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			C-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC677_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			C-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC678_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			G					74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC678_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			G					74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC678_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			G					74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC678_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			A10 				74HCXX:GATE			IN
11			A11 				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A12 				74HCXX:GATE			IN
14			A13 				74HCXX:GATE			IN
15			A14 				74HCXX:GATE			IN
16			A15 				74HCXX:GATE			IN
17			A16 				74HCXX:GATE			IN
18			P0  				74HCXX:GATE			IN
19			P1  				74HCXX:GATE			IN
20			P2  				74HCXX:GATE			IN
21			P3  				74HCXX:GATE			IN
22			Y					74HCXX:GATE			OUT
23			G					74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC679_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC679_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC679_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC679_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			G-  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC680_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			C					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC680_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			C					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC680_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			C					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC680_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			A2					74HCXX:GATE			IN
3			A3					74HCXX:GATE			IN
4			A4					74HCXX:GATE			IN
5			A5					74HCXX:GATE			IN
6			A6					74HCXX:GATE			IN
7			A7					74HCXX:GATE			IN
8			A8					74HCXX:GATE			IN
9			A9					74HCXX:GATE			IN
10			GND 				GND  					NA
11			A10 				74HCXX:GATE			IN
12			A11 				74HCXX:GATE			IN
13			A12 				74HCXX:GATE			IN
14			P0  				74HCXX:GATE			IN
15			P1  				74HCXX:GATE			IN
16			P2  				74HCXX:GATE			IN
17			P3  				74HCXX:GATE			IN
18			Y					74HCXX:GATE			OUT
19			C					74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC682_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC682_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC682_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC682_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC684_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC684_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC684_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC684_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			P>Q- 				74HCXX:GATE			OUT
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			P=Q-				74HCXX:GATE			OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC688_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			(P=Q)- 			74HCXX:LINE-DRV  	OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC688_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			(P=Q)- 			74HCXX:LINE-DRV  	OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC688_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			(P=Q)- 			74HCXX:LINE-DRV  	OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC688_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			G-					74HCXX:GATE			IN
2			P0					74HCXX:GATE			IN
3			Q0					74HCXX:GATE			IN
4			P1					74HCXX:GATE			IN
5			Q1					74HCXX:GATE			IN
6			P2					74HCXX:GATE			IN
7			Q2					74HCXX:GATE			IN
8			P3					74HCXX:GATE			IN
9			Q3					74HCXX:GATE			IN
10			GND 				GND  					NA
11			P4  				74HCXX:GATE			IN
12			Q4  				74HCXX:GATE			IN
13			P5  				74HCXX:GATE			IN
14			Q5  				74HCXX:GATE			IN
15			P6  				74HCXX:GATE			IN
16			Q6  				74HCXX:GATE			IN
17			P7  				74HCXX:GATE			IN
18			Q7  				74HCXX:GATE			IN
19			(P=Q)- 			74HCXX:LINE-DRV  	OUT
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC804_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC804_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC804_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC804_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC805_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC805_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC805_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC805_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC808_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC808_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC808_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC808_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC832_DIP
[Model File]		PML.MOD
[Package Model]    DIP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC832_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC832_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC832_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP20
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:LINE-DRV  	OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:LINE-DRV  	OUT
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:LINE-DRV  	OUT
10			GND 				GND  					NA
11			Y4  				74HCXX:LINE-DRV  	OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			Y5  				74HCXX:LINE-DRV  	OUT
15			A5  				74HCXX:GATE			IN
16			B5  				74HCXX:GATE			IN
17			Y6  				74HCXX:LINE-DRV  	OUT
18			A6  				74HCXX:GATE			IN
19			B6  				74HCXX:GATE			IN
20			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4002_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			D2					74HCXX:GATE			IN
10			C2  				74HCXX:GATE			IN
11			B2  				74HCXX:GATE			IN
12			A2  				74HCXX:GATE			IN
13			Y2  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4002_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			D2					74HCXX:GATE			IN
10			C2  				74HCXX:GATE			IN
11			B2  				74HCXX:GATE			IN
12			A2  				74HCXX:GATE			IN
13			Y2  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4002_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			D2					74HCXX:GATE			IN
10			C2  				74HCXX:GATE			IN
11			B2  				74HCXX:GATE			IN
12			A2  				74HCXX:GATE			IN
13			Y2  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4002_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			A1					74HCXX:GATE			IN
3			B2					74HCXX:GATE			IN
4			C2					74HCXX:GATE			IN
5			D3					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			D2					74HCXX:GATE			IN
10			C2  				74HCXX:GATE			IN
11			B2  				74HCXX:GATE			IN
12			A2  				74HCXX:GATE			IN
13			Y2  				74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4017_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y5					74HCXX:GATE			OUT
2			Y1					74HCXX:GATE			OUT
3			Y0					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y7					74HCXX:GATE			OUT
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y8					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			Y9  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			IN
13			CLKEN- 			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4017_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y5					74HCXX:GATE			OUT
2			Y1					74HCXX:GATE			OUT
3			Y0					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y7					74HCXX:GATE			OUT
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y8					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			Y9  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			IN
13			CLKEN- 			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4017_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y5					74HCXX:GATE			OUT
2			Y1					74HCXX:GATE			OUT
3			Y0					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y7					74HCXX:GATE			OUT
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Y8					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			Y9  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			IN
13			CLKEN- 			74HCXX:GATE			OUT
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4020_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4020_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4020_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4024_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK- 				74HCXX:GATE			IN
2			RESET				74HCXX:GATE			IN
3			Q7					74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q4					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			NC					NC						NA
9			Q3					74HCXX:GATE			OUT
10			NC  				NC						NA
11			Q2  				74HCXX:GATE			OUT
12			Q1  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4024_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK- 				74HCXX:GATE			IN
2			RESET				74HCXX:GATE			IN
3			Q7					74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q4					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			NC					NC						NA
9			Q3					74HCXX:GATE			OUT
10			NC  				NC						NA
11			Q2  				74HCXX:GATE			OUT
12			Q1  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4024_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK- 				74HCXX:GATE			IN
2			RESET				74HCXX:GATE			IN
3			Q7					74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q4					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			NC					NC						NA
9			Q3					74HCXX:GATE			OUT
10			NC  				NC						NA
11			Q2  				74HCXX:GATE			OUT
12			Q1  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4024_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			CLK- 				74HCXX:GATE			IN
2			RESET				74HCXX:GATE			IN
3			Q7					74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q4					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			NC					NC						NA
9			Q3					74HCXX:GATE			OUT
10			NC  				NC						NA
11			Q2  				74HCXX:GATE			OUT
12			Q1  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4040_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4040_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4040_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Q12  				74HCXX:GATE			OUT
2			Q13  				74HCXX:GATE			OUT
3			Q14  				74HCXX:GATE			OUT
4			Q6					74HCXX:GATE			OUT
5			Q5					74HCXX:GATE			OUT
6			Q7					74HCXX:GATE			OUT
7			Q4					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q1					74HCXX:GATE			OUT
10			CLK 				74HCXX:GATE			IN
11			RESET  			74HCXX:GATE			IN
12			Q9  				74HCXX:GATE			OUT
13			Q8  				74HCXX:GATE			OUT
14			Q10 				74HCXX:GATE			OUT
15			Q11 				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4046_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			PHASE_PLS  		74HCXX:GATE			OUT
2			PHASE_C1			ANALOG  				NA
3			COMPARATOR 		74HCXX:GATE			OUT
4			VCO  				74HCXX:GATE			OUT
5			INHIBIT 			74HCXX:GATE			IN
6			C1A  				ANALOG  				NA
7			C1B  				ANALOG  				NA
8			GND  				GND  					NA
9			VCO  				ANALOG  				NA
10			DEMOD  			74HCXX:GATE			IN
11			R1  				ANALOG  				NA
12			R2  				ANALOG  				NA
13			PHASE_C2  		ANALOG  				NA
14			SIGNAL 			74HCXX:GATE			OUT
15			PHASE_C3  		ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4046_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			PHASE_PLS  		74HCXX:GATE			OUT
2			PHASE_C1			ANALOG  				NA
3			COMPARATOR 		74HCXX:GATE			OUT
4			VCO  				74HCXX:GATE			OUT
5			INHIBIT 			74HCXX:GATE			IN
6			C1A  				ANALOG  				NA
7			C1B  				ANALOG  				NA
8			GND  				GND  					NA
9			VCO  				ANALOG  				NA
10			DEMOD  			74HCXX:GATE			IN
11			R1  				ANALOG  				NA
12			R2  				ANALOG  				NA
13			PHASE_C2  		ANALOG  				NA
14			SIGNAL 			74HCXX:GATE			OUT
15			PHASE_C3  		ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4049_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			VCC  				POWER					NA
2			A-					74HCXX:GATE			OUT
3			A 					74HCXX:GATE			IN
4			B-					74HCXX:GATE			OUT
5			B 					74HCXX:GATE			IN
6			C-					74HCXX:GATE			OUT
7			C 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D 					74HCXX:GATE			IN
10			D-  				74HCXX:GATE			OUT
11			E					74HCXX:GATE			IN
12			E-  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			F					74HCXX:GATE			IN
15			F-  				74HCXX:GATE			OUT
16			NC  				NC						NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4049_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			VCC  				POWER					NA
2			A-					74HCXX:GATE			OUT
3			A 					74HCXX:GATE			IN
4			B-					74HCXX:GATE			OUT
5			B 					74HCXX:GATE			IN
6			C-					74HCXX:GATE			OUT
7			C 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D 					74HCXX:GATE			IN
10			D-  				74HCXX:GATE			OUT
11			E					74HCXX:GATE			IN
12			E-  				74HCXX:GATE			OUT
13			NC  				NC						NA
14			F					74HCXX:GATE			IN
15			F-  				74HCXX:GATE			OUT
16			NC  				NC						NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4050_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			VCC  				POWER					NA
2			A 					74HCXX:GATE			OUT
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			OUT
5			B 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			OUT
7			C 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D 					74HCXX:GATE			IN
10			D					74HCXX:GATE			OUT
11			E					74HCXX:GATE			IN
12			E					74HCXX:GATE			OUT
13			NC  				NC						NA
14			F					74HCXX:GATE			IN
15			F					74HCXX:GATE			OUT
16			NC  				NC						NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4050_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			VCC  				POWER					NA
2			A 					74HCXX:GATE			OUT
3			A 					74HCXX:GATE			IN
4			B 					74HCXX:GATE			OUT
5			B 					74HCXX:GATE			IN
6			C 					74HCXX:GATE			OUT
7			C 					74HCXX:GATE			IN
8			GND  				GND  					NA
9			D 					74HCXX:GATE			IN
10			D					74HCXX:GATE			OUT
11			E					74HCXX:GATE			IN
12			E					74HCXX:GATE			OUT
13			NC  				NC						NA
14			F					74HCXX:GATE			IN
15			F					74HCXX:GATE			OUT
16			NC  				NC						NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4051_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y4					ANALOG  				NA
2			Y6					ANALOG  				NA
3			OUT/IN  			ANALOG  				NA
4			Y7					ANALOG  				NA
5			Y5					ANALOG  				NA
6			INH  				74HCXX:GATE			IN
7			VEE  				POWER					NA
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			Y3  				ANALOG  				NA
13			Y0  				ANALOG  				NA
14			Y1  				ANALOG  				NA
15			Y2  				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4051_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y4					ANALOG  				NA
2			Y6					ANALOG  				NA
3			OUT/IN  			ANALOG  				NA
4			Y7					ANALOG  				NA
5			Y5					ANALOG  				NA
6			INH  				74HCXX:GATE			IN
7			VEE  				POWER					NA
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			IN
11			A					74HCXX:GATE			IN
12			Y3  				ANALOG  				NA
13			Y0  				ANALOG  				NA
14			Y1  				ANALOG  				NA
15			Y2  				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4052_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y0					ANALOG  				NA
2			Y2					ANALOG  				NA
3			Y_OUT/IN			ANALOG  				NA
4			Y3					ANALOG  				NA
5			Y1					ANALOG  				NA
6			INH  				74HCXX:GATE			IN
7			VEE  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			X3  				ANALOG  				NA
12			X0  				ANALOG  				NA
13			X_OUT/IN  		ANALOG  				NA
14			X1  				ANALOG  				NA
15			X2  				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4052_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y0					ANALOG  				NA
2			Y2					ANALOG  				NA
3			Y_OUT/IN			ANALOG  				NA
4			Y3					ANALOG  				NA
5			Y1					ANALOG  				NA
6			INH  				74HCXX:GATE			IN
7			VEE  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			B 					74HCXX:GATE			IN
10			A					74HCXX:GATE			IN
11			X3  				ANALOG  				NA
12			X0  				ANALOG  				NA
13			X_OUT/IN  		ANALOG  				NA
14			X1  				ANALOG  				NA
15			X2  				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4053_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			BY					ANALOG  				NA
2			BX					ANALOG  				NA
3			CY					74HCXX:GATE			IN
4			C_OUT/IN			74HCXX:GATE			OUT
5			CX_IN/OUT  		74HCXX:GATE			IN
6			INH  				74HCXX:GATE			OUT
7			VEE  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			OUT
11			A					74HCXX:GATE			IN
12			AX  				ANALOG  				NA
13			AY  				ANALOG  				NA
14			A					ANALOG  				NA
15			B					ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4053_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			BY					ANALOG  				NA
2			BX					ANALOG  				NA
3			CY					74HCXX:GATE			IN
4			C_OUT/IN			74HCXX:GATE			OUT
5			CX_IN/OUT  		74HCXX:GATE			IN
6			INH  				74HCXX:GATE			OUT
7			VEE  				74HCXX:GATE			IN
8			GND  				GND  					NA
9			C 					74HCXX:GATE			IN
10			B					74HCXX:GATE			OUT
11			A					74HCXX:GATE			IN
12			AX  				ANALOG  				NA
13			AY  				ANALOG  				NA
14			A					ANALOG  				NA
15			B					ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4060_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4060_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4060_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4061_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4061_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4061_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			QL					74HCXX:GATE			OUT
2			QM					74HCXX:GATE			OUT
3			QN					74HCXX:GATE			OUT
4			QF					74HCXX:GATE			OUT
5			QE					74HCXX:GATE			OUT
6			QG					74HCXX:GATE			OUT
7			QD					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLKO 				74HCXX:GATE			IN
10			CLKO-  			74HCXX:GATE			IN
11			CLK_1  			74HCXX:GATE			IN
12			CLR 				74HCXX:GATE			IN
13			QI  				74HCXX:GATE			OUT
14			QH  				74HCXX:GATE			OUT
15			QJ  				74HCXX:GATE			OUT
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4075_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A2					74HCXX:GATE			IN
2			B2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			B3  				74HCXX:GATE			IN
13			C3  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4075_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A2					74HCXX:GATE			IN
2			B2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			B3  				74HCXX:GATE			IN
13			C3  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4075_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A2					74HCXX:GATE			IN
2			B2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			B3  				74HCXX:GATE			IN
13			C3  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4075_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A2					74HCXX:GATE			IN
2			B2					74HCXX:GATE			IN
3			A1					74HCXX:GATE			IN
4			B1					74HCXX:GATE			IN
5			C1					74HCXX:GATE			IN
6			Y1					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			B3  				74HCXX:GATE			IN
13			C3  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4078_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			K 					74HCXX:GATE			OUT
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			E 					74HCXX:GATE			IN
10			F					74HCXX:GATE			IN
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			Y					74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4078_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			K 					74HCXX:GATE			OUT
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			E 					74HCXX:GATE			IN
10			F					74HCXX:GATE			IN
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			Y					74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4078_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			K 					74HCXX:GATE			OUT
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			E 					74HCXX:GATE			IN
10			F					74HCXX:GATE			IN
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			Y					74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4078_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			K 					74HCXX:GATE			OUT
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			C 					74HCXX:GATE			IN
5			D 					74HCXX:GATE			IN
6			NC					NC						NA
7			GND  				GND  					NA
8			NC					NC						NA
9			E 					74HCXX:GATE			IN
10			F					74HCXX:GATE			IN
11			G					74HCXX:GATE			IN
12			H					74HCXX:GATE			IN
13			Y					74HCXX:GATE			OUT
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4351_DIP
[Model File]		PML.MOD
[Package Model]    DIP18
|
[Pin]		signal_name 	model_name  		direction
|
1			Y4					74HCXX:GATE			OUT
2			Y6					74HCXX:GATE			OUT
3			COM  				74HCXX:GATE			IN
4			Y5					74HCXX:GATE			OUT
5			Y7					74HCXX:GATE			OUT
6			INH  				74HCXX:GATE			IN
7			INH- 				74HCXX:GATE			IN
8			VEE  				74HCXX:GATE			IN
9			GND  				GND  					NA
10			LE- 				74HCXX:GATE			IN
11			C					74HCXX:GATE			IN
12			B					74HCXX:GATE			IN
13			A					74HCXX:GATE			IN
14			Y3  				74HCXX:GATE			OUT
15			Y0  				74HCXX:GATE			OUT
16			Y1  				74HCXX:GATE			OUT
17			Y2  				74HCXX:GATE			OUT
18			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4352_DIP
[Model File]		PML.MOD
[Package Model]    DIP18
|
[Pin]		signal_name 	model_name  		direction
|
1			Y0					74HCXX:GATE			OUT
2			Y2					74HCXX:GATE			OUT
3			COM_Y				74HCXX:GATE			OUT
4			Y3					74HCXX:GATE			OUT
5			Y1					74HCXX:GATE			OUT
6			INH  				74HCXX:GATE			IN
7			INH- 				74HCXX:GATE			IN
8			VEE  				74HCXX:GATE			IN
9			GND  				GND  					NA
10			LE- 				74HCXX:GATE			IN
11			B					74HCXX:GATE			IN
12			A					74HCXX:GATE			IN
13			X3  				74HCXX:GATE			IN
14			X0  				74HCXX:GATE			OUT
15			COM_X  			74HCXX:GATE			OUT
16			X1  				74HCXX:GATE			OUT
17			X2  				74HCXX:GATE			OUT
18			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4353_DIP
[Model File]		PML.MOD
[Package Model]    DIP18
|
[Pin]		signal_name 	model_name  		direction
|
1			YB					74HCXX:GATE			OUT
2			XB					74HCXX:GATE			IN
3			YC					74HCXX:GATE			OUT
4			COM_C				74HCXX:GATE			IN
5			XC					74HCXX:GATE			IN
6			INH  				74HCXX:GATE			IN
7			INH- 				74HCXX:GATE			IN
8			VEE  				74HCXX:GATE			IN
9			GND  				GND  					NA
10			LE- 				74HCXX:GATE			IN
11			C					74HCXX:GATE			IN
12			B					74HCXX:GATE			IN
13			A					74HCXX:GATE			IN
14			XA  				74HCXX:GATE			IN
15			YA  				74HCXX:GATE			OUT
16			COM_A  			74HCXX:GATE			IN
17			COM_B  			74HCXX:GATE			IN
18			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4514_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4514_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4514_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4514_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4515_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4515_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4515_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4515_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			STROBE  			74HCXX:GATE			IN
2			A 					74HCXX:GATE			IN
3			B 					74HCXX:GATE			IN
4			Y7					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			Y5					74HCXX:GATE			OUT
7			Y4					74HCXX:GATE			OUT
8			Y3					74HCXX:GATE			OUT
9			Y2					74HCXX:GATE			OUT
10			Y1  				74HCXX:GATE			OUT
11			Y0  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Y13 				74HCXX:GATE			OUT
14			Y12 				74HCXX:GATE			OUT
15			Y15 				74HCXX:GATE			OUT
16			Y14 				74HCXX:GATE			OUT
17			Y9  				74HCXX:GATE			OUT
18			Y8  				74HCXX:GATE			OUT
19			Y11 				74HCXX:GATE			OUT
20			Y10 				74HCXX:GATE			OUT
21			C					74HCXX:GATE			IN
22			D					74HCXX:GATE			IN
23			G-  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4538_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			T1A  				ANALOG  				NA
2			T2A  				ANALOG  				NA
3			CDA  				74HCXX:GATE			IN
4			A_A  				74HCXX:GATE			IN
5			B_A  				74HCXX:GATE			IN
6			QA					74HCXX:GATE			OUT
7			QA-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			QB-  				74HCXX:GATE			OUT
10			QB  				74HCXX:GATE			OUT
11			BB  				74HCXX:GATE			IN
12			AB  				74HCXX:GATE			IN
13			CDB 				74HCXX:GATE			IN
14			T2B 				ANALOG  				NA
15			T1B 				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4538_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			T1A  				ANALOG  				NA
2			T2A  				ANALOG  				NA
3			CDA  				74HCXX:GATE			IN
4			A_A  				74HCXX:GATE			IN
5			B_A  				74HCXX:GATE			IN
6			QA					74HCXX:GATE			OUT
7			QA-  				74HCXX:GATE			OUT
8			GND  				GND  					NA
9			QB-  				74HCXX:GATE			OUT
10			QB  				74HCXX:GATE			OUT
11			BB  				74HCXX:GATE			IN
12			AB  				74HCXX:GATE			IN
13			CDB 				74HCXX:GATE			IN
14			T2B 				ANALOG  				NA
15			T1B 				ANALOG  				NA
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4724_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4724_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC4724_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			S0					74HCXX:GATE			IN
2			S1					74HCXX:GATE			IN
3			S2					74HCXX:GATE			IN
4			Q0					74HCXX:GATE			OUT
5			Q1					74HCXX:GATE			OUT
6			Q2					74HCXX:GATE			OUT
7			Q3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			Q4					74HCXX:GATE			OUT
10			Q5  				74HCXX:GATE			OUT
11			Q6  				74HCXX:GATE			OUT
12			Q7  				74HCXX:GATE			OUT
13			D					74HCXX:GATE			IN
14			G-  				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7001_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7001_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7001_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7001_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7002_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7002_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7002_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7002_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7006_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			IN
7			B2					74HCXX:GATE			IN
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A4  				74HCXX:GATE			IN
14			Y4  				74HCXX:GATE			OUT
15			Y5  				74HCXX:GATE			OUT
16			A5  				74HCXX:GATE			IN
17			B5  				74HCXX:GATE			IN
18			C5  				74HCXX:GATE			IN
19			A6  				74HCXX:GATE			IN
20			B6  				74HCXX:GATE			IN
21			Y6  				74HCXX:GATE			OUT
22			C6  				74HCXX:GATE			IN
23			D6  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7006_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			IN
7			B2					74HCXX:GATE			IN
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A4  				74HCXX:GATE			IN
14			Y4  				74HCXX:GATE			OUT
15			Y5  				74HCXX:GATE			OUT
16			A5  				74HCXX:GATE			IN
17			B5  				74HCXX:GATE			IN
18			C5  				74HCXX:GATE			IN
19			A6  				74HCXX:GATE			IN
20			B6  				74HCXX:GATE			IN
21			Y6  				74HCXX:GATE			OUT
22			C6  				74HCXX:GATE			IN
23			D6  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7006_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			IN
7			B2					74HCXX:GATE			IN
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A4  				74HCXX:GATE			IN
14			Y4  				74HCXX:GATE			OUT
15			Y5  				74HCXX:GATE			OUT
16			A5  				74HCXX:GATE			IN
17			B5  				74HCXX:GATE			IN
18			C5  				74HCXX:GATE			IN
19			A6  				74HCXX:GATE			IN
20			B6  				74HCXX:GATE			IN
21			Y6  				74HCXX:GATE			OUT
22			C6  				74HCXX:GATE			IN
23			D6  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7006_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			C1					74HCXX:GATE			IN
5			D1					74HCXX:GATE			IN
6			A2					74HCXX:GATE			IN
7			B2					74HCXX:GATE			IN
8			C2					74HCXX:GATE			IN
9			Y2					74HCXX:GATE			OUT
10			Y3  				74HCXX:GATE			OUT
11			A3  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A4  				74HCXX:GATE			IN
14			Y4  				74HCXX:GATE			OUT
15			Y5  				74HCXX:GATE			OUT
16			A5  				74HCXX:GATE			IN
17			B5  				74HCXX:GATE			IN
18			C5  				74HCXX:GATE			IN
19			A6  				74HCXX:GATE			IN
20			B6  				74HCXX:GATE			IN
21			Y6  				74HCXX:GATE			OUT
22			C6  				74HCXX:GATE			IN
23			D6  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7008_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A5  				74HCXX:GATE			IN
14			Y5  				74HCXX:GATE			OUT
15			Y6  				74HCXX:GATE			OUT
16			A6  				74HCXX:GATE			IN
17			B6  				74HCXX:GATE			IN
18			A7  				74HCXX:GATE			IN
19			B7  				74HCXX:GATE			IN
20			Y7  				74HCXX:GATE			OUT
21			Y8  				74HCXX:GATE			OUT
22			A8  				74HCXX:GATE			IN
23			B8  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7008_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A5  				74HCXX:GATE			IN
14			Y5  				74HCXX:GATE			OUT
15			Y6  				74HCXX:GATE			OUT
16			A6  				74HCXX:GATE			IN
17			B6  				74HCXX:GATE			IN
18			A7  				74HCXX:GATE			IN
19			B7  				74HCXX:GATE			IN
20			Y7  				74HCXX:GATE			OUT
21			Y8  				74HCXX:GATE			OUT
22			A8  				74HCXX:GATE			IN
23			B8  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7008_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A5  				74HCXX:GATE			IN
14			Y5  				74HCXX:GATE			OUT
15			Y6  				74HCXX:GATE			OUT
16			A6  				74HCXX:GATE			IN
17			B6  				74HCXX:GATE			IN
18			A7  				74HCXX:GATE			IN
19			B7  				74HCXX:GATE			IN
20			Y7  				74HCXX:GATE			OUT
21			Y8  				74HCXX:GATE			OUT
22			A8  				74HCXX:GATE			IN
23			B8  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7008_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			A3					74HCXX:GATE			IN
8			B3					74HCXX:GATE			IN
9			Y3					74HCXX:GATE			OUT
10			Y4  				74HCXX:GATE			OUT
11			A4  				74HCXX:GATE			IN
12			GND 				GND  					NA
13			A5  				74HCXX:GATE			IN
14			Y5  				74HCXX:GATE			OUT
15			Y6  				74HCXX:GATE			OUT
16			A6  				74HCXX:GATE			IN
17			B6  				74HCXX:GATE			IN
18			A7  				74HCXX:GATE			IN
19			B7  				74HCXX:GATE			IN
20			Y7  				74HCXX:GATE			OUT
21			Y8  				74HCXX:GATE			OUT
22			A8  				74HCXX:GATE			IN
23			B8  				74HCXX:GATE			IN
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7022_DIP
[Model File]		PML.MOD
[Package Model]    DIP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y0					74HCXX:GATE			OUT
3			Y2					74HCXX:GATE			OUT
4			Y5					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			XCAP 				74HCXX:GATE			IN
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLR_O				74HCXX:GATE			OUT
10			Y7  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			OUT
13			CLKEN- 			74HCXX:GATE			IN
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7022_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y0					74HCXX:GATE			OUT
3			Y2					74HCXX:GATE			OUT
4			Y5					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			XCAP 				74HCXX:GATE			IN
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLR_O				74HCXX:GATE			OUT
10			Y7  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			OUT
13			CLKEN- 			74HCXX:GATE			IN
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7022_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP16
|
[Pin]		signal_name 	model_name  		direction
|
1			Y1					74HCXX:GATE			OUT
2			Y0					74HCXX:GATE			OUT
3			Y2					74HCXX:GATE			OUT
4			Y5					74HCXX:GATE			OUT
5			Y6					74HCXX:GATE			OUT
6			XCAP 				74HCXX:GATE			IN
7			Y3					74HCXX:GATE			OUT
8			GND  				GND  					NA
9			CLR_O				74HCXX:GATE			OUT
10			Y7  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			CO  				74HCXX:GATE			OUT
13			CLKEN- 			74HCXX:GATE			IN
14			CLK 				74HCXX:GATE			IN
15			CLR 				74HCXX:GATE			IN
16			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7032_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7032_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7032_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7032_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			A2					74HCXX:GATE			IN
5			B2					74HCXX:GATE			IN
6			Y2					74HCXX:GATE			OUT
7			GND  				GND  					NA
8			Y3					74HCXX:GATE			OUT
9			A3					74HCXX:GATE			IN
10			B3  				74HCXX:GATE			IN
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7074_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7074_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7074_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7074_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7075_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7075_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7075_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7075_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7076_DIP
[Model File]		PML.MOD
[Package Model]    DIP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7076_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7076_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7076_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP24
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			Y2					74HCXX:GATE			OUT
3			A3					74HCXX:GATE			IN
4			B3					74HCXX:GATE			IN
5			Y3					74HCXX:GATE			OUT
6			CLK4 				74HCXX:GATE			IN
7			PRE4-				74HCXX:GATE			IN
8			D4					74HCXX:GATE			IN
9			Q4-  				74HCXX:GATE			OUT
10			CLR4				74HCXX:GATE			IN
11			Q4  				74HCXX:GATE			OUT
12			GND 				GND  					NA
13			Q5  				74HCXX:GATE			OUT
14			CLR5-  			74HCXX:GATE			IN
15			Q5- 				74HCXX:GATE			OUT
16			D5  				74HCXX:GATE			IN
17			PRE5-  			74HCXX:GATE			IN
18			CLK5				74HCXX:GATE			IN
19			Y6  				74HCXX:GATE			OUT
20			A6  				74HCXX:GATE			IN
21			B6  				74HCXX:GATE			IN
22			A2  				74HCXX:GATE			IN
23			Y1  				74HCXX:GATE			OUT
24			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7266_DIP
[Model File]		PML.MOD
[Package Model]    DIP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7266_SOIC
[Model File]		PML.MOD
[Package Model]    SOIC14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7266_SSOP
[Model File]		PML.MOD
[Package Model]    SSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|==============================================================================
[Component]			74HC7266_TSSOP
[Model File]		PML.MOD
[Package Model]    TSSOP14
|
[Pin]		signal_name 	model_name  		direction
|
1			A1					74HCXX:GATE			IN
2			B1					74HCXX:GATE			IN
3			Y1					74HCXX:GATE			OUT
4			Y2					74HCXX:GATE			OUT
5			A2					74HCXX:GATE			IN
6			B2					74HCXX:GATE			IN
7			GND  				GND  					NA
8			A3					74HCXX:GATE			IN
9			B3					74HCXX:GATE			IN
10			Y3  				74HCXX:GATE			OUT
11			Y4  				74HCXX:GATE			OUT
12			A4  				74HCXX:GATE			IN
13			B4  				74HCXX:GATE			IN
14			VCC 				POWER					NA
|
|==============================================================================
|
[End]